cache_bram.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   cache_bram.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Cache storage in Xilinx BlockRAM
 *  
 *	Note: for correct operation, read-before-write functionality is required, 
 *  i.e. when writing, the _previous_ value of the written cell is output to DO
 *  this is achieved by setting synthesis attribute on RAMB16_S36_S36 (WRITE_MODE=READ_FIRST)
 *
 */

#ifndef CACHEMEM_H_INCLUDED
#define CACHEMEM_H_INCLUDED

#include <systemc.h>
#include "cache_dim.h"
#include "xlxram.h"

SC_MODULE(CACHE_BRAM_WRAP)
{
  sc_in<bool> clk;
  sc_in< sc_bv<32> > din;
  sc_in< bool > valid_in;
  sc_in< sc_bv<TAG_BITS> > tagi;
  sc_in< sc_bv<INDEX_BITS> > index;
  sc_in< sc_bv<OFFSET_BITS> > offset;
  sc_in< bool > we;
  sc_in< bool > en;  
  
  sc_out< sc_bv<32> > dout;
  sc_out< sc_bv<TAG_BITS> > tago;
  sc_out< bool > valid;

  sc_in<sc_int<32> > DOA0, DOB0, DOA1, DOB1;
  sc_in<sc_int<4> > DOPA0, DOPB0, DOPA1, DOPB1;
  sc_out<sc_uint<9> > ADDRA0, ADDRB0, ADDRA1, ADDRB1;
  sc_out<sc_int<32> > DIA0, DIB0, DIA1, DIB1;
  sc_out<sc_int<4> > DIPA0, DIPB0, DIPA1, DIPB1;
  sc_out<bool> ENA0, ENB0, ENA1, ENB1;
  sc_out<bool> CLKA0, CLKB0, CLKA1, CLKB1;
  sc_out<bool> WEA0, WEB0, WEA1, WEB1;
  sc_out<bool> SSRA0, SSRB0, SSRA1, SSRB1;

  sc_signal< sc_uint<2> > word;
  
  void reg();
  void in();
  void out();
  
  SC_CTOR(CACHE_BRAM_WRAP)
	{
	  SC_METHOD(in);
	  sensitive << clk << din << valid_in << tagi << index << offset << we << en;
	  SC_METHOD(out);
	  sensitive << word << DOA0 << DOPA0 << DOB0 << DOPB0 << DOA1 << DOPA1 << DOB1 << DOPB1;
	  SC_METHOD(reg);
	  sensitive_pos << clk;
 	}
};


SC_MODULE(CACHE_MEMORY)
{	
  sc_in<bool> clk;
  sc_in< sc_bv<32> > din;
  sc_in< bool > valid_in;
  sc_in< sc_bv<TAG_BITS> > tagi;
  sc_in< sc_bv<INDEX_BITS> > index;
  sc_in< sc_bv<OFFSET_BITS> > offset;
  sc_in< bool > we;
  sc_in< bool > en;  
  
  sc_out< sc_bv<32> > dout;
  sc_out< sc_bv<TAG_BITS> > tago;
  sc_out< bool > valid;  
  
  CACHE_BRAM_WRAP *wrap;
  RAMB16_S36_S36 *bram0, *bram1;

  sc_signal<sc_int<32> > DOA0, DOB0, DOA1, DOB1;
  sc_signal<sc_int<4> > DOPA0, DOPB0, DOPA1, DOPB1;
  sc_signal<sc_uint<9> > ADDRA0, ADDRB0, ADDRA1, ADDRB1;
  sc_signal<sc_int<32> > DIA0, DIB0, DIA1, DIB1;
  sc_signal<sc_int<4> > DIPA0, DIPB0, DIPA1, DIPB1;
  sc_signal<bool> ENA0, ENB0, ENA1, ENB1;
  sc_signal<bool> CLKA0, CLKB0, CLKA1, CLKB1;
  sc_signal<bool> WEA0, WEB0, WEA1, WEB1;
  sc_signal<bool> SSRA0, SSRB0, SSRA1, SSRB1;
  
  SC_CTOR(CACHE_MEMORY)
	{
	  wrap = new CACHE_BRAM_WRAP("wrap");
	  bram0 = new RAMB16_S36_S36("bram0");
	  bram1 = new RAMB16_S36_S36("bram1");
	  
	  wrap->clk(clk);
	  wrap->din(din);
	  wrap->valid_in(valid_in);
	  wrap->tagi(tagi);
	  wrap->index(index);
	  wrap->offset(offset);
	  wrap->we(we);
	  wrap->en(en);
	  wrap->dout(dout);
	  wrap->tago(tago);
	  wrap->valid(valid);
	  
	  wrap->DOA0(DOA0); wrap->DOB0(DOB0); wrap->DOA1(DOA1); wrap->DOB1(DOB1);
	  wrap->DOPA0(DOPA0); wrap->DOPB0(DOPB0); wrap->DOPA1(DOPA1); wrap->DOPB1(DOPB1);
	  wrap->ADDRA0(ADDRA0); wrap->ADDRB0(ADDRB0); wrap->ADDRA1(ADDRA1); wrap->ADDRB1(ADDRB1);
	  wrap->DIA0(DIA0); wrap->DIB0(DIB0); wrap->DIA1(DIA1); wrap->DIB1(DIB1);
	  wrap->DIPA0(DIPA0); wrap->DIPB0(DIPB0); wrap->DIPA1(DIPA1); wrap->DIPB1(DIPB1);
	  wrap->ENA0(ENA0); wrap->ENB0(ENB0); wrap->ENA1(ENA1); wrap->ENB1(ENB1);
	  wrap->CLKA0(CLKA0); wrap->CLKB0(CLKB0); wrap->CLKA1(CLKA1); wrap->CLKB1(CLKB1);
	  wrap->WEA0(WEA0); wrap->WEB0(WEB0); wrap->WEA1(WEA1); wrap->WEB1(WEB1);
	  wrap->SSRA0(SSRA0); wrap->SSRB0(SSRB0); wrap->SSRA1(SSRA1); wrap->SSRB1(SSRB1);

	  bram0->DOA(DOA0); bram0->DOB(DOB0); bram1->DOA(DOA1); bram1->DOB(DOB1);
	  bram0->DOPA(DOPA0); bram0->DOPB(DOPB0); bram1->DOPA(DOPA1); bram1->DOPB(DOPB1);
	  bram0->ADDRA(ADDRA0); bram0->ADDRB(ADDRB0); bram1->ADDRA(ADDRA1); bram1->ADDRB(ADDRB1);
	  bram0->DIA(DIA0); bram0->DIB(DIB0); bram1->DIA(DIA1); bram1->DIB(DIB1);
	  bram0->DIPA(DIPA0); bram0->DIPB(DIPB0); bram1->DIPA(DIPA1); bram1->DIPB(DIPB1);
	  bram0->ENA(ENA0); bram0->ENB(ENB0); bram1->ENA(ENA1); bram1->ENB(ENB1);
	  bram0->CLKA(CLKA0); bram0->CLKB(CLKB0); bram1->CLKA(CLKA1); bram1->CLKB(CLKB1);
	  bram0->WEA(WEA0); bram0->WEB(WEB0); bram1->WEA(WEA1); bram1->WEB(WEB1);
	  bram0->SSRA(SSRA0); bram0->SSRB(SSRB0); bram1->SSRA(SSRA1); bram1->SSRB(SSRB1);
	  
	}
    
};

#endif