mem32k.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   mem32k.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   32kB RAM based on VirtexII 16kb BlockRAMs
 *                      Uses 16 blocks of 2-bit-wide memory
 *
 */
 
#ifndef MEM32K_H_INCLUDED
#define MEM32K_H_INCLUDED

#include "xlxram.h"

SC_MODULE(MEM32K_WRAPPER) {
	sc_in <	sc_uint<32> > addr;
	sc_out< sc_int<32> > dout;
	sc_in< sc_int<32> > din;
	sc_in< bool > ww, wb, r;
	sc_in< bool > clk;	

	sc_out<sc_uint<13> > ADDR;
	sc_out<sc_int<2> > DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07, 
	  DI08, DI09, DI10, DI11, DI12, DI13, DI14, DI15;
	sc_out<bool> EN, CLK, SSR, WE0, WE1, WE2, WE3;
	sc_in<sc_int<2> > DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07, 
	  DO08, DO09, DO10, DO11, DO12, DO13, DO14, DO15;
	
	void in();
	void out();
	
	SC_CTOR(MEM32K_WRAPPER) {
	  
	  SC_METHOD(in);
	  sensitive << addr << din << ww << wb << r << clk;
	  
	  SC_METHOD(out);
	  sensitive << DO00 << DO01 << DO02 << DO03 << DO04 << DO05 << DO06 << DO07 
				<< DO08 << DO09 << DO10 << DO11 << DO12 << DO13 << DO14 << DO15 ;

	};
	
};

// Converter for the debugging access
SC_MODULE(MEM32K_DBGWRAPPER) {

  sc_out<sc_int<32> > DO;
  sc_in<sc_uint<32> > ADDR;
  sc_in<sc_int<32> > DI;
  sc_in<bool> EN;
  sc_in<bool> CLK;
  sc_in<bool> WE;
  sc_in<bool> RST;

  sc_out<sc_uint<13> > dADDR;
  sc_out<sc_int<2> > dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07, 
	dDI08, dDI09, dDI10, dDI11, dDI12, dDI13, dDI14, dDI15;
  sc_out<bool> dEN, dCLK, dSSR, dWE;
  sc_in<sc_int<2> > dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07, 
	dDO08, dDO09, dDO10, dDO11, dDO12, dDO13, dDO14, dDO15;

  void in();
  void out();
	
  SC_CTOR(MEM32K_DBGWRAPPER) {  
	SC_METHOD(in);
	sensitive << ADDR << DI << EN << WE << RST << CLK;
	  
	SC_METHOD(out);
	sensitive << dDO00 << dDO01 << dDO02 << dDO03 << dDO04 << dDO05 << dDO06 << dDO07 
			  << dDO08 << dDO09 << dDO10 << dDO11 << dDO12 << dDO13 << dDO14 << dDO15 ;
  };
	
};

SC_MODULE(MEM32K) {
	sc_in <	sc_uint<32> > addr;
	sc_out< sc_int<32> > dout;
	sc_in< sc_int<32> > din;
	sc_in< bool > ww, wb, r;
	sc_in< bool > clk;	

	// memory bits - bram00 keeps bit at address 00, so its MSB (BIGENDIAN)
	RAMB16_S2_S2 *bram00, *bram01, *bram02, *bram03, *bram04, 
	  *bram05, *bram06, *bram07, *bram08, 
	  *bram09, *bram10, *bram11, *bram12, 
	  *bram13, *bram14, *bram15;
	MEM32K_WRAPPER *conv;
	
	sc_signal<sc_uint<13> > ADDR;
	sc_signal<sc_int<2> > DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07, 
	  DI08, DI09, DI10, DI11, DI12, DI13, DI14, DI15;
	sc_signal<bool> EN, CLK, SSR, WE0, WE1, WE2, WE3;
	sc_signal<sc_int<2> > DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07, 
	  DO08, DO09, DO10, DO11, DO12, DO13, DO14, DO15;
	MEM32K_DBGWRAPPER *dbgconv;
	
	// independent access to the second set of ports for debugging
	
	sc_out<sc_int<32> > dbgDO;
	sc_in<sc_uint<32> > dbgADDR;
	sc_in<sc_int<32> > dbgDI;
	sc_in<bool> dbgEN;
	sc_in<bool> dbgCLK;
	sc_in<bool> dbgWE;
	sc_in<bool> dbgRST;

	sc_signal<sc_uint<13> > dADDR;
	sc_signal<sc_int<2> > dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07, 
	  dDI08, dDI09, dDI10, dDI11, dDI12, dDI13, dDI14, dDI15;
	sc_signal<bool> dEN, dCLK, dSSR, dWE;
	sc_signal<sc_int<2> > dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07, 
	  dDO08, dDO09, dDO10, dDO11, dDO12, dDO13, dDO14, dDO15;	
#ifndef VERILOG
	void mem_init(const char *filename, int size=32768);
	void mem_dump(const char *filename, int size=32768);
#endif

	SC_CTOR(MEM32K) {

	  bram00 = new RAMB16_S2_S2("bram00");
	  bram01 = new RAMB16_S2_S2("bram01");
	  bram02 = new RAMB16_S2_S2("bram02");
	  bram03 = new RAMB16_S2_S2("bram03");
	  bram04 = new RAMB16_S2_S2("bram04");
	  bram05 = new RAMB16_S2_S2("bram05");
	  bram06 = new RAMB16_S2_S2("bram06");
	  bram07 = new RAMB16_S2_S2("bram07");
	  bram08 = new RAMB16_S2_S2("bram08");
	  bram09 = new RAMB16_S2_S2("bram09");
	  bram10 = new RAMB16_S2_S2("bram10");
	  bram11 = new RAMB16_S2_S2("bram11");
	  bram12 = new RAMB16_S2_S2("bram12");
	  bram13 = new RAMB16_S2_S2("bram13");
	  bram14 = new RAMB16_S2_S2("bram14");
	  bram15 = new RAMB16_S2_S2("bram15");

	  conv = new MEM32K_WRAPPER("conv");
	  conv->addr(addr);
	  conv->din(din);
	  conv->dout(dout);
	  conv->r(r);
	  conv->ww(ww);
	  conv->wb(wb);
	  conv->clk(clk);

	  dbgconv = new MEM32K_DBGWRAPPER("dbgconv");
	  dbgconv->DO(dbgDO);
	  dbgconv->ADDR(dbgADDR);
	  dbgconv->DI(dbgDI);
	  dbgconv->EN(dbgEN);
	  dbgconv->CLK(dbgCLK);
	  dbgconv->WE(dbgWE);
	  dbgconv->RST(dbgRST);

	  
	  bram00->ADDRA(ADDR); bram00->ENA(EN); bram00->WEA(WE0); bram00->CLKA(CLK); bram00->SSRA(SSR);
	  bram01->ADDRA(ADDR); bram01->ENA(EN); bram01->WEA(WE0); bram01->CLKA(CLK); bram01->SSRA(SSR);
	  bram02->ADDRA(ADDR); bram02->ENA(EN); bram02->WEA(WE0); bram02->CLKA(CLK); bram02->SSRA(SSR);
	  bram03->ADDRA(ADDR); bram03->ENA(EN); bram03->WEA(WE0); bram03->CLKA(CLK); bram03->SSRA(SSR);
	  bram04->ADDRA(ADDR); bram04->ENA(EN); bram04->WEA(WE1); bram04->CLKA(CLK); bram04->SSRA(SSR);
	  bram05->ADDRA(ADDR); bram05->ENA(EN); bram05->WEA(WE1); bram05->CLKA(CLK); bram05->SSRA(SSR);
	  bram06->ADDRA(ADDR); bram06->ENA(EN); bram06->WEA(WE1); bram06->CLKA(CLK); bram06->SSRA(SSR);
	  bram07->ADDRA(ADDR); bram07->ENA(EN); bram07->WEA(WE1); bram07->CLKA(CLK); bram07->SSRA(SSR);
	  bram08->ADDRA(ADDR); bram08->ENA(EN); bram08->WEA(WE2); bram08->CLKA(CLK); bram08->SSRA(SSR);
	  bram09->ADDRA(ADDR); bram09->ENA(EN); bram09->WEA(WE2); bram09->CLKA(CLK); bram09->SSRA(SSR);
	  bram10->ADDRA(ADDR); bram10->ENA(EN); bram10->WEA(WE2); bram10->CLKA(CLK); bram10->SSRA(SSR);
	  bram11->ADDRA(ADDR); bram11->ENA(EN); bram11->WEA(WE2); bram11->CLKA(CLK); bram11->SSRA(SSR);
	  bram12->ADDRA(ADDR); bram12->ENA(EN); bram12->WEA(WE3); bram12->CLKA(CLK); bram12->SSRA(SSR);
	  bram13->ADDRA(ADDR); bram13->ENA(EN); bram13->WEA(WE3); bram13->CLKA(CLK); bram13->SSRA(SSR);
	  bram14->ADDRA(ADDR); bram14->ENA(EN); bram14->WEA(WE3); bram14->CLKA(CLK); bram14->SSRA(SSR);
	  bram15->ADDRA(ADDR); bram15->ENA(EN); bram15->WEA(WE3); bram15->CLKA(CLK); bram15->SSRA(SSR);
	  

	  bram00->DIA(DI00); bram00->DOA(DO00);
	  bram01->DIA(DI01); bram01->DOA(DO01);
	  bram02->DIA(DI02); bram02->DOA(DO02);
	  bram03->DIA(DI03); bram03->DOA(DO03);
	  bram04->DIA(DI04); bram04->DOA(DO04);
	  bram05->DIA(DI05); bram05->DOA(DO05);
	  bram06->DIA(DI06); bram06->DOA(DO06);
	  bram07->DIA(DI07); bram07->DOA(DO07);
	  bram08->DIA(DI08); bram08->DOA(DO08);
	  bram09->DIA(DI09); bram09->DOA(DO09);
	  bram10->DIA(DI10); bram10->DOA(DO10);
	  bram11->DIA(DI11); bram11->DOA(DO11);
	  bram12->DIA(DI12); bram12->DOA(DO12);
	  bram13->DIA(DI13); bram13->DOA(DO13);
	  bram14->DIA(DI14); bram14->DOA(DO14);
	  bram15->DIA(DI15); bram15->DOA(DO15);

	  conv->ADDR(ADDR); conv->EN(EN); conv->CLK(CLK); conv->SSR(SSR);
	  conv->WE3(WE3);
	  conv->WE2(WE2);
	  conv->WE1(WE1);
	  conv->WE0(WE0);
	  conv->DI00(DI00); conv->DO00(DO00);
	  conv->DI01(DI01); conv->DO01(DO01);
	  conv->DI02(DI02); conv->DO02(DO02);
	  conv->DI03(DI03); conv->DO03(DO03);
	  conv->DI04(DI04); conv->DO04(DO04);
	  conv->DI05(DI05); conv->DO05(DO05);
	  conv->DI06(DI06); conv->DO06(DO06);
	  conv->DI07(DI07); conv->DO07(DO07);
	  conv->DI08(DI08); conv->DO08(DO08);
	  conv->DI09(DI09); conv->DO09(DO09);
	  conv->DI10(DI10); conv->DO10(DO10);
	  conv->DI11(DI11); conv->DO11(DO11);
	  conv->DI12(DI12); conv->DO12(DO12);
	  conv->DI13(DI13); conv->DO13(DO13);
	  conv->DI14(DI14); conv->DO14(DO14);
	  conv->DI15(DI15); conv->DO15(DO15);
	  

	  bram00->ADDRB(dADDR); bram00->ENB(dEN); bram00->WEB(dWE); bram00->CLKB(dCLK); bram00->SSRB(dSSR);
	  bram01->ADDRB(dADDR); bram01->ENB(dEN); bram01->WEB(dWE); bram01->CLKB(dCLK); bram01->SSRB(dSSR);
	  bram02->ADDRB(dADDR); bram02->ENB(dEN); bram02->WEB(dWE); bram02->CLKB(dCLK); bram02->SSRB(dSSR);
	  bram03->ADDRB(dADDR); bram03->ENB(dEN); bram03->WEB(dWE); bram03->CLKB(dCLK); bram03->SSRB(dSSR);
	  bram04->ADDRB(dADDR); bram04->ENB(dEN); bram04->WEB(dWE); bram04->CLKB(dCLK); bram04->SSRB(dSSR);
	  bram05->ADDRB(dADDR); bram05->ENB(dEN); bram05->WEB(dWE); bram05->CLKB(dCLK); bram05->SSRB(dSSR);
	  bram06->ADDRB(dADDR); bram06->ENB(dEN); bram06->WEB(dWE); bram06->CLKB(dCLK); bram06->SSRB(dSSR);
	  bram07->ADDRB(dADDR); bram07->ENB(dEN); bram07->WEB(dWE); bram07->CLKB(dCLK); bram07->SSRB(dSSR);
	  bram08->ADDRB(dADDR); bram08->ENB(dEN); bram08->WEB(dWE); bram08->CLKB(dCLK); bram08->SSRB(dSSR);
	  bram09->ADDRB(dADDR); bram09->ENB(dEN); bram09->WEB(dWE); bram09->CLKB(dCLK); bram09->SSRB(dSSR);
	  bram10->ADDRB(dADDR); bram10->ENB(dEN); bram10->WEB(dWE); bram10->CLKB(dCLK); bram10->SSRB(dSSR);
	  bram11->ADDRB(dADDR); bram11->ENB(dEN); bram11->WEB(dWE); bram11->CLKB(dCLK); bram11->SSRB(dSSR);
	  bram12->ADDRB(dADDR); bram12->ENB(dEN); bram12->WEB(dWE); bram12->CLKB(dCLK); bram12->SSRB(dSSR);
	  bram13->ADDRB(dADDR); bram13->ENB(dEN); bram13->WEB(dWE); bram13->CLKB(dCLK); bram13->SSRB(dSSR);
	  bram14->ADDRB(dADDR); bram14->ENB(dEN); bram14->WEB(dWE); bram14->CLKB(dCLK); bram14->SSRB(dSSR);
	  bram15->ADDRB(dADDR); bram15->ENB(dEN); bram15->WEB(dWE); bram15->CLKB(dCLK); bram15->SSRB(dSSR);

	  bram00->DIB(dDI00); bram00->DOB(dDO00);
	  bram01->DIB(dDI01); bram01->DOB(dDO01);
	  bram02->DIB(dDI02); bram02->DOB(dDO02);
	  bram03->DIB(dDI03); bram03->DOB(dDO03);
	  bram04->DIB(dDI04); bram04->DOB(dDO04);
	  bram05->DIB(dDI05); bram05->DOB(dDO05);
	  bram06->DIB(dDI06); bram06->DOB(dDO06);
	  bram07->DIB(dDI07); bram07->DOB(dDO07);
	  bram08->DIB(dDI08); bram08->DOB(dDO08);
	  bram09->DIB(dDI09); bram09->DOB(dDO09);
	  bram10->DIB(dDI10); bram10->DOB(dDO10);
	  bram11->DIB(dDI11); bram11->DOB(dDO11);
	  bram12->DIB(dDI12); bram12->DOB(dDO12);
	  bram13->DIB(dDI13); bram13->DOB(dDO13);
	  bram14->DIB(dDI14); bram14->DOB(dDO14);
	  bram15->DIB(dDI15); bram15->DOB(dDO15);

	  dbgconv->dADDR(dADDR); dbgconv->dEN(dEN); dbgconv->dWE(dWE); dbgconv->dCLK(dCLK); dbgconv->dSSR(dSSR);
	  dbgconv->dDI00(dDI00); dbgconv->dDO00(dDO00);
	  dbgconv->dDI01(dDI01); dbgconv->dDO01(dDO01);
	  dbgconv->dDI02(dDI02); dbgconv->dDO02(dDO02);
	  dbgconv->dDI03(dDI03); dbgconv->dDO03(dDO03);
	  dbgconv->dDI04(dDI04); dbgconv->dDO04(dDO04);
	  dbgconv->dDI05(dDI05); dbgconv->dDO05(dDO05);
	  dbgconv->dDI06(dDI06); dbgconv->dDO06(dDO06);
	  dbgconv->dDI07(dDI07); dbgconv->dDO07(dDO07);
	  dbgconv->dDI08(dDI08); dbgconv->dDO08(dDO08);
	  dbgconv->dDI09(dDI09); dbgconv->dDO09(dDO09);
	  dbgconv->dDI10(dDI10); dbgconv->dDO10(dDO10);
	  dbgconv->dDI11(dDI11); dbgconv->dDO11(dDO11);
	  dbgconv->dDI12(dDI12); dbgconv->dDO12(dDO12);
	  dbgconv->dDI13(dDI13); dbgconv->dDO13(dDO13);
	  dbgconv->dDI14(dDI14); dbgconv->dDO14(dDO14);
	  dbgconv->dDI15(dDI15); dbgconv->dDO15(dDO15);
 
	};
};


#endif