📄 mmips.h
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/*
* TU Eindhoven
* Eindhoven, The Netherlands
*
* Name : mmips.h
*
* Author : A.S.Slusarczyk@tue.nl
*
* Updated : Jose Prats - jprats@step.es
*
* Function : Top-level mMIPS module
*/
#ifndef MMIPS_H_INCLUDED
#define MMIPS_H_INCLUDED
#include "add.h"
#include "aluctrl.h"
#include "alu.h"
#include "branch.h"
#include "ctrl.h"
#include "decoder.h"
#include "hazard.h"
#include "imm2word.h"
#include "mux.h"
#include "register.h"
#include "shift.h"
#include "signextend.h"
#include "bram16k.h"
#include "brom16k.h"
#include "bregisterfile16.h"
#include "memdev.h"
#include "translator_mmips.h"
#ifdef CACHE
#define ICACHE
#define DCACHE
#include "cache.h"
#endif
#ifdef USEXRAM
#include "xram.h"
#endif
SC_MODULE(CLKDIST){
sc_in<bool> clkin;
sc_out<bool> clkout;
SC_CTOR(CLKDIST){
SC_METHOD(clk);
sensitive << clkin;
}
void clk(){
clkout.write(clkin.read());
}
};
SC_MODULE(mMIPS)
{
sc_in<bool> clock;
sc_in<bool> enable;
sc_in<bool> reset;
sc_signal<bool> clk;
sc_signal<bool> bus_enable;
/*
* SIGNALS
*/
sc_out< sc_bv<DWORD> > bus_pc;
// Data signals
sc_signal< sc_bv<DWORD> > bus_mux1;
sc_signal< sc_bv<DWORD> > bus_mux2;
sc_signal< sc_bv<DWORD> > bus_mux3;
sc_signal< sc_bv<AWORDREG> > bus_mux4;
sc_signal< sc_bv<DWORD> > bus_mux5;
sc_signal< sc_bv<DWORD> > bus_mux6;
sc_signal< sc_bv<6> > bus_decoder_instr_31_26;
sc_signal< sc_bv<DWORD> > bus_decoder_instr_25_0;
sc_signal< sc_bv<AWORDREG> > bus_decoder_instr_25_21;
sc_signal< sc_bv<AWORDREG> > bus_decoder_instr_20_16;
sc_signal< sc_bv<AWORDREG> > bus_decoder_instr_15_11;
sc_signal< sc_bv<16> > bus_decoder_instr_15_0;
sc_signal< sc_bv<5> > bus_decoder_instr_10_6;
sc_signal< sc_bv<6> > bus_decoder_instr_5_0;
sc_signal< sc_bv<DWORD> > bus_add1;
sc_signal< sc_bv<DWORD> > bus_add2;
sc_signal< sc_bv<DWORD> > bus_shiftleft;
sc_signal< sc_bv<DWORD> > bus_shiftleft_jmp;
sc_signal< sc_bv<DWORD> > bus_imm2word;
sc_signal< sc_bv<DWORD> > bus_signextendbyte;
sc_signal< sc_bv<DWORD> > bus_imem_1;
sc_signal< sc_bv<DWORD> > bus_dmem_1;
sc_signal< sc_bv<DWORD> > bus_alu_result;
sc_signal< sc_bv<1> > bus_alu_zero;
sc_signal< sc_bv<DWORD> > bus_registers_1;
sc_signal< sc_bv<DWORD> > bus_registers_2;
// Control signals
sc_signal< sc_bv<W_REGDST> > bus_ctrl_regdst;
sc_signal< sc_bv<W_REGVAL> > bus_ctrl_regvalue;
sc_signal< sc_bv<W_TARGET> > bus_ctrl_target;
sc_signal< sc_bv<W_BRANCHOP> > bus_ctrl_branch;
sc_signal< sc_bv<W_MEMREAD> > bus_ctrl_memread;
sc_signal< sc_bv<W_MEMTOREG> > bus_ctrl_memtoreg;
sc_signal< sc_bv<W_ALUOP> > bus_ctrl_aluop;
sc_signal< sc_bv<W_MEMWRITE> > bus_ctrl_memwrite;
sc_signal< sc_bv<W_ALUSRC> > bus_ctrl_alusrc;
sc_signal< sc_bv<W_REGWRITE> > bus_ctrl_regwrite;
sc_signal< sc_bv<W_SIGNEXTEND> > bus_ctrl_signextend;
sc_signal< sc_bv<DWORD> > bus_ctrl_c4;
sc_signal< sc_bv<1> > bus_ctrl_c1;
sc_signal< sc_bv<AWORDREG> > bus_ctrl_c31;
sc_signal< sc_bv<1> > bus_ctrl_enable;
sc_signal< sc_bv<1> > bus_pipe_en, bus_dmem_en, bus_imem_en;
sc_signal< sc_bv<W_ALUCTRL> > bus_aluctrl;
sc_signal< sc_bv<W_BRANCHFLAG> > bus_branch;
// Signals needed for pipelining
// Instruction fecth -> Instruction decode
sc_signal< sc_bv<DWORD> > bus_if_pc;
sc_signal< sc_bv<DWORD> > bus_if_instr;
// Instruction decode -> Execution
sc_signal< sc_bv<DWORD> > bus_id_pc;
sc_signal< sc_bv<DWORD> > bus_id_data_reg1;
sc_signal< sc_bv<DWORD> > bus_id_data_reg2;
sc_signal< sc_bv<DWORD> > bus_id_immediate;
sc_signal< sc_bv<DWORD> > bus_id_instr_25_0;
sc_signal< sc_bv<AWORDREG> > bus_id_instr_20_16;
sc_signal< sc_bv<AWORDREG> > bus_id_instr_15_11;
sc_signal< sc_bv<6> > bus_id_instr_5_0;
sc_signal< sc_bv<5> > bus_id_instr_10_6;
sc_signal< sc_bv<W_ALUSRC> > bus_id_ctrl_ex_alusrc;
sc_signal< sc_bv<W_ALUOP> > bus_id_ctrl_ex_aluop;
sc_signal< sc_bv<W_REGDST> > bus_id_ctrl_ex_regdst;
sc_signal< sc_bv<W_REGVAL> > bus_id_ctrl_ex_regvalue;
sc_signal< sc_bv<W_TARGET> > bus_id_ctrl_ex_target;
sc_signal< sc_bv<W_BRANCHOP> > bus_id_ctrl_mem_branch;
sc_signal< sc_bv<W_MEMWRITE> > bus_id_ctrl_mem_memwrite;
sc_signal< sc_bv<W_MEMREAD> > bus_id_ctrl_mem_memread;
sc_signal< sc_bv<W_REGWRITE> > bus_id_ctrl_wb_regwrite;
sc_signal< sc_bv<W_MEMTOREG> > bus_id_ctrl_wb_memtoreg;
// Execution -> Memory stage
sc_signal< sc_bv<AWORDREG> > bus_ex_regdst_addr;
sc_signal< sc_bv<DWORD> > bus_ex_alu_result;
sc_signal< sc_bv<W_REGWRITE> > bus_ex_ctrl_wb_regwrite;
sc_signal< sc_bv<W_MEMTOREG> > bus_ex_ctrl_wb_memtoreg;
// Memory stage -> Write back stage
sc_signal< sc_bv<DWORD> > bus_mem_dmem_data;
sc_signal< sc_bv<DWORD> > bus_mem_alu_result;
sc_signal< sc_bv<AWORDREG> > bus_mem_regdst_addr;
sc_signal< sc_bv<W_REGWRITE> > bus_mem_ctrl_wb_regwrite;
sc_signal< sc_bv<W_MEMTOREG> > bus_mem_ctrl_wb_memtoreg;
// Hazard detection unit
sc_signal< sc_bv<W_PCWRITEFLAG> > bus_hazard_pcwrite;
sc_signal< sc_bv<W_IFIDWRITEFLAG> > bus_hazard_ifidwrite;
sc_signal< sc_bv<W_HAZARDFLAG> > bus_hazard_hazard;
sc_signal< sc_bv<W_REGDST> > bus_ctrl2hazard_regdst;
sc_signal< sc_bv<W_REGVAL> > bus_ctrl2hazard_regvalue;
sc_signal< sc_bv<W_TARGET> > bus_ctrl2hazard_target;
sc_signal< sc_bv<W_BRANCHOP> > bus_ctrl2hazard_branch;
sc_signal< sc_bv<W_MEMREAD> > bus_ctrl2hazard_memread;
sc_signal< sc_bv<W_MEMTOREG> > bus_ctrl2hazard_memtoreg;
sc_signal< sc_bv<W_ALUOP> > bus_ctrl2hazard_aluop;
sc_signal< sc_bv<W_MEMWRITE> > bus_ctrl2hazard_memwrite;
sc_signal< sc_bv<W_ALUSRC> > bus_ctrl2hazard_alusrc;
sc_signal< sc_bv<W_REGWRITE> > bus_ctrl2hazard_regwrite;
/*
* MODULES
*/
#ifndef VERILOG
// Pipeline registers
// Instruction fecth -> Instruction decode
REGISTER<DWORD> *if_pc;
REGISTER<DWORD> *if_instr;
// Instruction decode -> Execution
REGISTER<DWORD> *id_pc;
REGISTER<DWORD> *id_data_reg1;
REGISTER<DWORD> *id_data_reg2;
REGISTER<DWORD> *id_immediate;
REGISTER<DWORD> *id_instr_25_0;
REGISTER<AWORDREG> *id_instr_20_16;
REGISTER<AWORDREG> *id_instr_15_11;
REGISTER<6> *id_instr_5_0;
REGISTER<5> *id_instr_10_6;
REGISTER<W_ALUSRC> *id_ctrl_ex_alusrc;
REGISTER<W_ALUOP> *id_ctrl_ex_aluop;
REGISTER<W_REGDST> *id_ctrl_ex_regdst;
REGISTER<W_REGVAL> *id_ctrl_ex_regvalue;
REGISTER<W_TARGET> *id_ctrl_ex_target;
REGISTER<W_BRANCHOP> *id_ctrl_mem_branch;
REGISTER<W_MEMWRITE> *id_ctrl_mem_memwrite;
REGISTER<W_MEMREAD> *id_ctrl_mem_memread;
REGISTER<W_REGWRITE> *id_ctrl_wb_regwrite;
REGISTER<W_MEMTOREG> *id_ctrl_wb_memtoreg;
// Execution -> Memory stage
REGISTER<AWORDREG> *ex_regdst_addr;
REGISTER<DWORD> *ex_alu_result;
REGISTER<W_REGWRITE> *ex_ctrl_wb_regwrite;
REGISTER<W_MEMTOREG> *ex_ctrl_wb_memtoreg;
// Memory stage -> Write back stage
REGISTER<DWORD> *mem_dmem_data;
REGISTER<DWORD> *mem_alu_result;
REGISTER<AWORDREG> *mem_regdst_addr;
REGISTER<W_REGWRITE> *mem_ctrl_wb_regwrite;
REGISTER<W_MEMTOREG> *mem_ctrl_wb_memtoreg;
// program counter
REGISTER<DWORD> *pc;
#else // VERILOG
// Pipeline registers
// Instruction fecth - Instruction decode
REGISTER_DWORD *if_pc;
REGISTER_DWORD *if_instr;
// Instruction decode - Execution
REGISTER_DWORD *id_pc;
REGISTER_DWORD *id_data_reg1;
REGISTER_DWORD *id_data_reg2;
REGISTER_DWORD *id_immediate;
REGISTER_DWORD *id_instr_25_0;
REGISTER_AWORDREG *id_instr_20_16;
REGISTER_AWORDREG *id_instr_15_11;
REGISTER_6 *id_instr_5_0;
REGISTER_5 *id_instr_10_6;
REGISTER_W_ALUSRC *id_ctrl_ex_alusrc;
REGISTER_W_ALUOP *id_ctrl_ex_aluop;
REGISTER_W_REGDST *id_ctrl_ex_regdst;
REGISTER_W_REGVAL *id_ctrl_ex_regvalue;
REGISTER_W_TARGET *id_ctrl_ex_target;
REGISTER_W_BRANCHOP *id_ctrl_mem_branch;
REGISTER_W_MEMWRITE *id_ctrl_mem_memwrite;
REGISTER_W_MEMREAD *id_ctrl_mem_memread;
REGISTER_W_REGWRITE *id_ctrl_wb_regwrite;
REGISTER_W_MEMTOREG *id_ctrl_wb_memtoreg;
// Execution - Memory stage
REGISTER_AWORDREG *ex_regdst_addr;
REGISTER_DWORD *ex_alu_result;
REGISTER_W_REGWRITE *ex_ctrl_wb_regwrite;
REGISTER_W_MEMTOREG *ex_ctrl_wb_memtoreg;
// Memory stage - Write back stage
REGISTER_DWORD *mem_dmem_data;
REGISTER_DWORD *mem_alu_result;
REGISTER_AWORDREG *mem_regdst_addr;
REGISTER_W_REGWRITE *mem_ctrl_wb_regwrite;
REGISTER_W_MEMTOREG *mem_ctrl_wb_memtoreg;
// program counter
REGISTER_DWORD *pc;
#endif
// Hazard handling
HAZARD *hazard;
HAZARD_CTRL *hazard_ctrl;
// Branch handling
BRANCH_CTRL *branch_ctrl;
// Modules used for computation
ADD *add1;
ADD *add2;
#ifdef ICACHE
DATA_CACHE *imem;
sc_out< sc_bv<32> > icache_addr, icache_din;
sc_in< sc_bv<32> > icache_dout;
sc_out< bool > icache_ww, icache_wb, icache_r;
sc_in< bool > icache_rdy;
sc_signal< sc_bv<W_MEMWRITE> > c0_imem_w;
sc_signal< sc_bv<W_MEMREAD> > c1_imem_r;
sc_signal< sc_bv<DWORD> > c0_imem_din;
#else
BROM16K *imem;
sc_out<sc_int<32> > romDO;
sc_in<sc_uint<32> > romADDR;
sc_in<sc_int<32> > romDI;
sc_in<bool> romEN;
sc_in<bool> romCLK;
sc_in<bool> romWE;
sc_in<bool> romRST;
#endif
#ifdef DCACHE
DATA_CACHE *dmem;
sc_out< sc_bv<32> > dcache_addr, dcache_din;
sc_in< sc_bv<32> > dcache_dout;
sc_out< bool > dcache_ww, dcache_wb, dcache_r;
sc_in< bool > dcache_rdy;
#else
BRAM16K *dmem;
sc_out<sc_int<32> > ramDO;
sc_in<sc_uint<32> > ramADDR;
sc_in<sc_int<32> > ramDI;
sc_in<bool> ramEN;
sc_in<bool> ramCLK;
sc_in<bool> ramWE;
sc_in<bool> ramRST;
#endif
REGFILE16 *registers;
ALU *alu;
ALUCTRL *aluctrl;
IMM2WORD *imm2word;
SIGNEXTEND_BYTE *signextendbyte;
SHIFTLEFT *shiftleft;
SHIFTLEFT *shiftleft_jmp;
CTRL *ctrl;
DECODER *decoder;
sc_signal< sc_bv<AWORDREG> > bus_decoder_nb_instr_25_21;
sc_signal< sc_bv<AWORDREG> > bus_decoder_nb_instr_20_16;
DECODER_NBUF *decoder_nb;
MUX2 *mux7;
sc_signal< sc_bv<DWORD> > bus_mux7;
MUX2 *mux1;
MUX2 *mux2;
MUX3 *mux3;
MUX3_AWORDREG *mux4;
MUX3 *mux5;
MUX2 *mux6;
CLKDIST *clkdist;
// memory-mapped-device infrostructure
MEMDEV *memdev;
sc_out< sc_bv<DWORD> > dev_dout;
sc_in< sc_bv<DWORD> > dev_din;
sc_out< bool > dev_r, dev_w;
sc_in< bool > dev_rdyr, dev_rdyw;
sc_out< bool > dev_wdata, dev_waddr;
sc_out<bool> dev_send_eop;
sc_in<bool> dev_rcv_eop;
sc_signal< sc_bv<DWORD> > bus_dev_din;
sc_signal< bool > bus_dev_r, bus_dev_w;
sc_signal< bool > bus_dev_wdata, bus_dev_waddr;
sc_signal<bool> bus_dev_send_eop;
sc_signal< sc_bv<DWORD> > bus_ram_din, bus_ram_addr, bus_ram_dout, ram_dout;
sc_signal< bool > bus_ram_wait;
sc_signal< sc_bv<W_MEMREAD> > bus_ram_r;
sc_signal< sc_bv<W_MEMWRITE> > bus_ram_w;
sc_signal< bool > bus_dmem_wait;
sc_signal< bool > bus_imem_wait;
//TRANSLATOR: It manages the communication between mMIPS node and memory node.
TRANSLATOR_MMIPS *translator_mmips;
sc_in < sc_int<8> > x_mem_addr;
sc_in < sc_int<8> > y_mem_addr;
sc_in < sc_int<8> > my_xaddr;
sc_in < sc_int<8> > my_yaddr;
sc_in < sc_int<8> > xdimension;
sc_in < sc_int<8> > ydimension;
/*sc_in< bool > dev_w, dev_r;
sc_in< sc_bv<DWORD> > dev_din;
sc_in< bool > dev_wdata, dev_waddr;
sc_in< bool > dev_send_eop;*/
/*sc_in< sc_bv<2> > ram_w;
sc_in< sc_bv<2> > ram_r;
sc_in< sc_bv<DWORD> > ram_addr;
sc_in< sc_bv<DWORD> > ram_din; */
/*sc_in< sc_bv<32> > reg_data_out; // dev_din (in) From NI
sc_in< bool > data_rdy; // dev_rdyr (in)
sc_in< bool > send_rdy; */ // dev_rdyw (in)
/*sc_out< bool > trans_dev_w, trans_dev_r; //To NI
sc_out< sc_bv<DWORD> > trans_dev_din;
sc_out< bool > trans_dev_wdata, trans_dev_waddr;
sc_out< bool > trans_dev_send_eop;*/
sc_signal< sc_bv<W_MEMWRITE> > local_ram_w; //To local memory
sc_signal< sc_bv<W_MEMREAD> > local_ram_r;
sc_signal< bool > enable_mmips; // To the control of the mMIPS
sc_signal < sc_bv<32> > trans_ram_dout; //To the MEMDEV ⌨️ 快捷键说明
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