brom4k.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   brom4k.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Xilinx-Block-RAM-based ROM
 *
 *
 */
 
#ifndef BROM4K_H_INCLUDED
#define BROM4K_H_INCLUDED

#include "mips.h"
#include "xlxram.h"

// wrapper around BlockRAM memory
SC_MODULE(ROM4KCONV) {
	sc_in <	sc_bv<DWORD> > addr;
	sc_out< sc_bv<DWORD> > dout;
	sc_out< bool > memwait;
	sc_in<	bool		 > memclk;
	sc_in<	sc_bv<1>	 > en;

	sc_in<sc_int<32> > DO;
	sc_in<sc_int<4> > DOP;
	sc_out<sc_uint<9> > ADDR;
	sc_out<sc_int<32> > DI;
	sc_out<sc_int<4> > DIP;
	sc_out<bool> EN;
	sc_out<bool> CLK;
	sc_out<bool> WE;
	sc_out<bool> SSR;

	void clock();
	void in();
	void out();
	
	SC_CTOR(ROM4KCONV) {
	  
	  SC_METHOD(in);
	  sensitive << addr << en;
	  
	  SC_METHOD(out);
	  sensitive << DO << DOP;

	  SC_METHOD(clock);
	  sensitive << memclk;
	};
	
};

// Converter for the debugging access
SC_MODULE(DBGBROM4KCONV) {

  sc_out<sc_int<32> > DO;
  sc_in<sc_uint<32> > ADDR;
  sc_in<sc_int<32> > DI;
  sc_in<bool> EN;
  sc_in<bool> CLK;
  sc_in<bool> WE;
  sc_in<bool> RST;

  sc_in<sc_int<32> > mDO;
  sc_in<sc_int<4> > mDOP;
  sc_out<sc_uint<9> > mADDR;
  sc_out<sc_int<32> > mDI;
  sc_out<sc_int<4> > mDIP;
  sc_out<bool> mEN;
  sc_out<bool> mCLK;
  sc_out<bool> mWE;
  sc_out<bool> mSSR;

  void in();
  void out();
	
  SC_CTOR(DBGBROM4KCONV) {  
	SC_METHOD(in);
	sensitive << ADDR << DI << EN << WE << RST << CLK;
	  
	SC_METHOD(out);
	sensitive << mDO << mDOP;
  };
	
};

SC_MODULE(ROM4K) {
	sc_in <	sc_bv<DWORD> > addr;
	sc_out< sc_bv<DWORD> > dout;
	sc_in<	bool		 > clk;
	sc_out< bool > memwait;

	sc_in<	sc_bv<1>	 > en;
	
	RAMB16_S36_S36 *bram;
	ROM4KCONV *conv;
	
	sc_signal<sc_int<32> > DO;
	sc_signal<sc_int<4> > DOP, DIP;
	sc_signal<sc_uint<9> > ADDR;
	sc_signal<sc_int<32> > DI;
	sc_signal<bool> EN;
	sc_signal<bool> CLK;
	sc_signal<bool> WE;
	sc_signal<bool> SSR;

	DBGBROM4KCONV *dbgconv;
	
	sc_out<sc_int<32> > dbgDO;
	sc_in<sc_uint<32> > dbgADDR;
	sc_in<sc_int<32> > dbgDI;
	sc_in<bool> dbgEN;
	sc_in<bool> dbgCLK;
	sc_in<bool> dbgWE;
	sc_in<bool> dbgRST;

	sc_signal<sc_int<32> > dDO;
	sc_signal<sc_int<4> > dDOP, dDIP;
	sc_signal<sc_uint<9> > dADDR;
	sc_signal<sc_int<32> > dDI;
	sc_signal<bool> dEN;
	sc_signal<bool> dCLK;
	sc_signal<bool> dWE;
	sc_signal<bool> dSSR;

#ifndef VERILOG
	void mem_init(const char *filename);
	void mem_dump(const char *filename);
#endif
	
	SC_CTOR(ROM4K) {
	  bram = new RAMB16_S36_S36("bram");
	  conv = new ROM4KCONV("conv");
	  
	  
	  bram->DOA(DO);
	  conv->DO(DO);
	  bram->DOPA(DOP);
	  conv->DOP(DOP);
	  bram->ADDRA(ADDR);
	  conv->ADDR(ADDR);
	  bram->DIA(DI);
	  conv->DI(DI);
	  bram->DIPA(DIP);
	  conv->DIP(DIP);
	  bram->ENA(EN);
	  conv->EN(EN);
	  bram->CLKA(CLK);
	  conv->CLK(CLK);
	  bram->WEA(WE);
	  conv->WE(WE);
	  bram->SSRA(SSR);
	  conv->SSR(SSR);
	  
	  conv->addr(addr);
	  conv->dout(dout);
	  conv->memwait(memwait);
	  conv->memclk(clk);	  
	  conv->en(en);

	  dbgconv = new DBGBROM4KCONV("dbgconv");

	  dbgconv->DO(dbgDO);
	  dbgconv->ADDR(dbgADDR);
	  dbgconv->DI(dbgDI);
	  dbgconv->EN(dbgEN);
	  dbgconv->CLK(dbgCLK);
	  dbgconv->WE(dbgWE);
	  dbgconv->RST(dbgRST);
	  
	  bram->DOB(dDO);	  dbgconv->mDO(dDO);
	  bram->DOPB(dDOP);	  dbgconv->mDOP(dDOP);
	  bram->ADDRB(dADDR);	  dbgconv->mADDR(dADDR);
	  bram->DIB(dDI);	  dbgconv->mDI(dDI);
	  bram->DIPB(dDIP);	  dbgconv->mDIP(dDIP);
	  bram->ENB(dEN);	  dbgconv->mEN(dEN);
	  bram->CLKB(dCLK);	  dbgconv->mCLK(dCLK);
	  bram->WEB(dWE);	  dbgconv->mWE(dWE);
	  bram->SSRB(dSSR);	  dbgconv->mSSR(dSSR);

	};
};

#endif