main.cpp

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   main.cpp
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Simulation testbench for a single mMIPS (with or without cache)
 *
 */
 

// undefine NOVCD to enable tracing of mMIPS internal signals
#define NOVCD 1

#ifdef CACHE
#include "cache_mips.h"
#else
#include "mmips.h"
#endif

#include "mips_trace.h"
// 
//  MAIN
//

int sc_main(int argc, char *argv[])
{
  char stbuf[256];
  sc_signal<bool> clk;
  sc_signal< bool > rst, en;
  unsigned sim_time = 0, period = 20;

  // the processor
#ifdef CACHE
  CACHE_MIPS mips("mips");
#else
  mMIPS mips("mips");
#endif
  
  mips.clock(clk);
  mips.reset(rst);
  mips.enable(en);

  // PC for monitoring
  sc_signal< sc_bv<DWORD> > bus_pc;
  mips.bus_pc(bus_pc);

  
  // initialize memories and connect  
  // memory debugging ports (unused in simulation)
  
#ifdef CACHE
  mips.memory->memory->mem_init("mem.bin", ROMSIZE+RAMSIZE);
  mips.memory->memory->mem_dump("mem.0.dump", ROMSIZE+RAMSIZE);
#else
  mips.dmem->mem_init("mips_ram.bin");
  mips.dmem->mem_dump("mips_ram.0.dump");
  mips.imem->mem_init("mips_rom.bin");
  mips.imem->mem_dump("mips_rom.0.dump");
#endif

  sc_signal<sc_int<32> > ramDO;
  sc_signal<sc_uint<32> > ramADDR;
  sc_signal<sc_int<32> > ramDI;
  sc_signal<bool> ramEN, ramCLK, ramWE, ramRST;

  mips.ramDO(ramDO);
  mips.ramADDR(ramADDR);
  mips.ramDI(ramDI);
  mips.ramEN(ramEN);
  mips.ramCLK(ramCLK);
  mips.ramWE(ramWE);
  mips.ramRST(ramRST);

  sc_signal<sc_int<32> > romDO;
  sc_signal<sc_uint<32> > romADDR;
  sc_signal<sc_int<32> > romDI;
  sc_signal<bool> romEN, romCLK, romWE, romRST;

  mips.romDO(romDO);
  mips.romADDR(romADDR);
  mips.romDI(romDI);
  mips.romEN(romEN);
  mips.romCLK(romCLK);
  mips.romWE(romWE);
  mips.romRST(romRST);



  // unused network device interface
  sc_signal< sc_bv<DWORD> > dev_dout;
  sc_signal< sc_bv<DWORD> > dev_din;
  sc_signal< bool > dev_r, dev_w;
  sc_signal< bool > dev_rdyr, dev_rdyw;
  sc_signal< bool > dev_wdata, dev_waddr;
  sc_signal< bool > dev_send_eop, dev_rcv_eop;

  mips.dev_dout(dev_dout);
  mips.dev_din(dev_din);
  mips.dev_r(dev_r);
  mips.dev_w(dev_w);
  mips.dev_rdyr(dev_rdyr);
  mips.dev_rdyw(dev_rdyw);
  mips.dev_wdata(dev_wdata);
  mips.dev_waddr(dev_waddr);
  mips.dev_send_eop(dev_send_eop);
  mips.dev_rcv_eop(dev_rcv_eop);

#ifdef USEXRAM
  sc_signal< sc_int<32> > xDO;
  sc_signal< sc_uint<32> > xADDR;
  sc_signal< bool > xCLK, xWE;
  
  mips.xDO(xDO);
  mips.xADDR(xADDR);
  mips.xCLK(xCLK);
  mips.xWE(xWE);
#endif


#ifndef NOVCD
  /*
   *	Tracing
   */
  sc_trace_file *tf;
  tf = sc_create_vcd_trace_file("mips");

#ifdef CACHE
  mMIPS *mmips = mips.mips;
#else
  mMIPS *mmips = &mips;
#endif
  
  trace_mips( tf, mmips, "mips.");

#ifdef CACHE
  trace_cache( tf, mmips->dmem, "data_cache.");
  trace_cache( tf, mmips->imem, "instr_cache.");
  trace_mainmem( tf, mips.memory, "cache_mainmem.");
#endif
  
#endif  
  
  /*********************************************************************************
	Start simulation
  *********************************************************************************/
  
  sc_initialize();
  
  // reset and enable the system
  clk = 0; rst = 1; en = 0; 
  sc_cycle(period/2);
  clk = 1; 
  sc_cycle(period/2);
  rst = 0;

  clk = 0; 
  sc_cycle(period/2);
  en = 1;

  /*
   *	Simulate program execution
   */
  int max_time = 0;
  if (argc == 2) max_time = atoi(argv[1]);
  if (max_time == 0) max_time = 500;

  unsigned pc;

  // run until simulation time or pc==16 
  while( max_time < 0 || sim_time < (unsigned)max_time )
	{
	  clk = 0;
	  sc_cycle(period/2);
	  clk = 1;
	  sc_cycle(period/2);
	  sim_time += period;
	  
	  pc = sc_uint<32>(bus_pc.read());
	  if( pc == 0x10 ) { cout << "END: " << sim_time/period << " cycles" << endl; break; }
	}
	

#ifdef CACHE
  mips.memory->memory->mem_dump("mem.dump",RAMSIZE+ROMSIZE);
#else
  mips.dmem->mem_dump("mips_ram.dump");
#endif

#ifndef NOVCD
  sc_close_vcd_trace_file(tf);
#endif
  return 0;
}