xram.h

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   xram.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Hardware-trace memory (XRAM) 
 *                      and the signal collection module (SIGNAL_DBG)
 */
 
#ifndef XRAM_H_INCLUDED
#define XRAM_H_INCLUDED

#include "mips.h"
#include "xlxram.h"

// converter from the XRAM-interface to Xilinx BlockRAMs
SC_MODULE(XRAMCONV) 
{

  sc_out<sc_int<32> > DO;
  sc_in<sc_uint<32> > ADDR;
  sc_in<sc_int<32> > DI;
  sc_in< bool > CLK;

  sc_in< sc_uint<11> > addr_cnt;

  sc_in<sc_int<8> > DO0, DO1, DO2, DO3;
  sc_out<sc_int<8> > DI0, DI1, DI2, DI3;
  sc_out<sc_uint<11> > wADDR, rADDR;
  sc_out<bool> wCLK;

  void in(){
	wADDR.write( (sc_uint<21>(0), addr_cnt.read()) );
	rADDR.write( ADDR.read() );
	DI3.write( sc_int<8>(DI.read().range(7,0)) );
	DI2.write( sc_int<8>(DI.read().range(15,8)) );
	DI1.write( sc_int<8>(DI.read().range(23,16)) );
	DI0.write( sc_int<8>(DI.read().range(31,24)) );
	wCLK.write( !CLK.read() );
  }
  void out(){
	DO.write( ( DO0.read(), DO1.read(), DO2.read(), DO3.read()) );
  }
		
  SC_CTOR(XRAMCONV) {
	SC_METHOD(in);
	sensitive << ADDR << DI << addr_cnt << CLK;
	SC_METHOD(out);
	sensitive << DO0 << DO1 << DO2 << DO3;
  };
};

// automatic address counter for XRAM 
// note - it DOES NOT wrap
SC_MODULE(XRAM_CNT){
  sc_in<bool> clk, en;
  sc_out< sc_uint<11> > cnt;
  
  SC_CTOR(XRAM_CNT){
	SC_METHOD(c);
	sensitive_pos << clk;
  }
  
  void c(){
	if( en.read() && (cnt.read()!=0x7ff) )
	  cnt.write( cnt.read()+1 );
  }
};

// the trace memory
SC_MODULE(XRAM)
{  
  sc_out<sc_int<32> > DO;
  sc_in<sc_uint<32> > ADDR;
  sc_in<sc_int<32> > DI;
  sc_in<bool> CLK;
  sc_in<bool> WE;

  RAMB16_S9_S9 *bram0, *bram1, *bram2, *bram3;
  XRAMCONV *conv;
  XRAM_CNT *cnt;
  sc_signal< sc_uint<11> > addr_cnt;
	
  sc_signal<sc_int<8> > DO0, DO1, DO2, DO3;
  sc_signal<sc_int<8> > DI0, DI1, DI2, DI3;
  sc_signal<sc_uint<11> > wADDR, rADDR;
  sc_signal<bool> wWE, wCLK;

  sc_signal< sc_int<8> > zero8, out;
  sc_signal< sc_int<1> > zero1, pout;
  sc_signal< sc_uint<11> > zero11;
  sc_signal< bool > zero, one;

#ifndef VERILOG
  void mem_dump(const char *filename){
	vector<sc_int<8>* > v;
	v.push_back(bram3->memory);
	v.push_back(bram2->memory);
	v.push_back(bram1->memory);
	v.push_back(bram0->memory);
	dump_memory(&v,8192,filename);
  }
#endif
	
  SC_CTOR(XRAM) {
	bram0 = new RAMB16_S9_S9("bram0");
	bram1 = new RAMB16_S9_S9("bram1");
	bram2 = new RAMB16_S9_S9("bram2");
	bram3 = new RAMB16_S9_S9("bram3");
	conv = new XRAMCONV("conv");
	cnt = new XRAM_CNT("cnt");
	  
	zero8 = 0;
	zero11 = 0;
	zero1 = 0;
	zero = 0;
	one = 1;
	  
	cnt->clk(wCLK);
	cnt->en(WE);
	cnt->cnt(addr_cnt);
	  	  
	conv->ADDR(ADDR);
	conv->addr_cnt(addr_cnt);
	conv->DI(DI);
	conv->wADDR(wADDR);
	conv->rADDR(rADDR);
	conv->DO(DO);
	conv->CLK(CLK);
	conv->wCLK(wCLK);

	conv->DO0(DO0);
	conv->DO1(DO1);
	conv->DO2(DO2);
	conv->DO3(DO3);
	
	conv->DI0(DI0);
	conv->DI1(DI1);
	conv->DI2(DI2);
	conv->DI3(DI3);

	// writing to port A
	bram0->DIA(DI0); bram1->DIA(DI1); bram2->DIA(DI2); bram3->DIA(DI3);
	bram0->ADDRA(wADDR); bram1->ADDRA(wADDR); bram2->ADDRA(wADDR); bram3->ADDRA(wADDR);
	bram0->ENA(one); bram1->ENA(one); bram2->ENA(one); bram3->ENA(one);
	bram0->WEA(WE); bram1->WEA(WE); bram2->WEA(WE); bram3->WEA(WE);
	bram0->CLKA(wCLK); bram1->CLKA(wCLK); bram2->CLKA(wCLK); bram3->CLKA(wCLK);

	bram0->DOA(out); bram1->DOA(out); bram2->DOA(out); bram3->DOA(out);
	bram0->SSRA(zero); bram1->SSRA(zero); bram2->SSRA(zero); bram3->SSRA(zero);
	bram0->DOPA(pout); bram1->DOPA(pout); bram2->DOPA(pout); bram3->DOPA(pout);
	bram0->DIPA(zero1); bram1->DIPA(zero1); bram2->DIPA(zero1); bram3->DIPA(zero1);

	// reading from port B
	bram0->DOB(DO0); bram1->DOB(DO1); bram2->DOB(DO2); bram3->DOB(DO3);
	bram0->ADDRB(rADDR); bram1->ADDRB(rADDR); bram2->ADDRB(rADDR); bram3->ADDRB(rADDR);
	bram0->ENB(one); bram1->ENB(one); bram2->ENB(one); bram3->ENB(one);
	bram0->CLKB(CLK); bram1->CLKB(CLK); bram2->CLKB(CLK); bram3->CLKB(CLK);

	bram0->DIB(zero8); bram1->DIB(zero8); bram2->DIB(zero8); bram3->DIB(zero8);
	bram0->DOPB(pout); bram1->DOPB(pout); bram2->DOPB(pout); bram3->DOPB(pout);
	bram0->DIPB(zero1); bram1->DIPB(zero1); bram2->DIPB(zero1); bram3->DIPB(zero1);
	bram0->WEB(zero); bram1->WEB(zero); bram2->WEB(zero); bram3->WEB(zero);
	bram0->SSRB(zero); bram1->SSRB(zero); bram2->SSRB(zero); bram3->SSRB(zero);
  };
};


// signal collection module : concatenates the connected signals to a single 32-bit signal DO
SC_MODULE(SIGNAL_DBG){
  
  sc_out< sc_int<32> > DO;
  
  sc_in< bool > clk;
  sc_in< sc_bv<1> > ctrl_enable;	
  sc_in< sc_bv<1> > ctrl_hazard_pcwrite; 
  sc_in< sc_bv<1> > ctrl_hazard_ifidwrite; 
  sc_in< sc_bv<1> > ctrl_hazard_hazard; 
  sc_in< sc_bv<1> > pipe_en;
  sc_in< sc_bv<1> > dmem_en;
  sc_in< sc_bv<1> > imem_en;
  sc_in< sc_bv<5> > decoder_nb_instr_20_16, decoder_nb_instr_25_21;
  
  sc_in<bool> clock, enable, reset;
  
  sc_in< sc_bv<32> > sig32;
  
  void join(){
	sc_bv<1> one(1);
	DO.write( (sc_int<1>(one),
			   sc_int<10>( sc_bv<10>(sig32.read().range(9,0)) ),
			   sc_int<5>(decoder_nb_instr_25_21.read()),
			   sc_int<5>(decoder_nb_instr_20_16.read()),
			   sc_int<1>(ctrl_hazard_hazard.read()),
			   sc_int<1>(ctrl_hazard_pcwrite.read()),
			   sc_int<1>(ctrl_hazard_ifidwrite.read()),
			   sc_int<1>(pipe_en.read()),
			   sc_int<1>(dmem_en.read()),
			   sc_int<1>(imem_en.read()),
			   sc_int<1>(ctrl_enable.read()),
			   sc_int<1>(clk.read()),
			   sc_int<1>(reset.read()),
			   sc_int<1>(enable.read()),
			   sc_int<1>(clock.read())
			   ) );
  }

  SC_CTOR(SIGNAL_DBG){
	SC_METHOD(join);
	sensitive << clk << ctrl_enable << ctrl_hazard_pcwrite << ctrl_hazard_ifidwrite << ctrl_hazard_hazard
			  << pipe_en << dmem_en << imem_en
			  << decoder_nb_instr_25_21 << decoder_nb_instr_20_16
			  << clock << enable << reset << sig32;
  }
};
#endif