_network2x2.cpp

改进的基于6个mips核的NOC网络

	NETWORK2x2 network2x2("network2x2");

	NETmMIPS dp_x0y0("dp_x0y0");
	NETmMIPS dp_x0y1("dp_x0y1");
	NETmMIPS dp_x1y0("dp_x1y0");
	//NETmMIPS dp_x1y1("dp_x1y1");
	NET_REMOTE_MEM dp_x1y1("dp_x1y1");  

	sc_signal< sc_bv<FLIT_LEN> > x0y0din;
	sc_signal< sc_bv<FLIT_LEN> > x0y0dout;
	sc_signal< bool > x0y0req_net;
	sc_signal< bool > x0y0ack_net;
	sc_signal< bool > x0y0ack_dp;
	sc_signal< bool > x0y0req_dp;

	sc_signal< sc_bv<FLIT_LEN> > x0y1din;
	sc_signal< sc_bv<FLIT_LEN> > x0y1dout;
	sc_signal< bool > x0y1req_net;
	sc_signal< bool > x0y1ack_net;
	sc_signal< bool > x0y1ack_dp;
	sc_signal< bool > x0y1req_dp;

	sc_signal< sc_bv<FLIT_LEN> > x1y0din;
	sc_signal< sc_bv<FLIT_LEN> > x1y0dout;
	sc_signal< bool > x1y0req_net;
	sc_signal< bool > x1y0ack_net;
	sc_signal< bool > x1y0ack_dp;
	sc_signal< bool > x1y0req_dp;

	sc_signal< sc_bv<FLIT_LEN> > x1y1din;
	sc_signal< sc_bv<FLIT_LEN> > x1y1dout;
	sc_signal< bool > x1y1req_net;
	sc_signal< bool > x1y1ack_net;
	sc_signal< bool > x1y1ack_dp;
	sc_signal< bool > x1y1req_dp;
	
	sc_signal< sc_int<8> > xdimension; //= "00000010";   
	sc_signal< sc_int<8> > ydimension; //= "00000010";
	sc_signal< sc_int<8> > x_mem_addr; //= "00000001";
	sc_signal< sc_int<8> > y_mem_addr; //7= "00000001";
	sc_signal< sc_int<8> > zero;       //= "00000000";
	sc_signal< sc_int<8> > one;        //= "00000001";
	
	xdimension.write(2);	
	ydimension.write(2);
	x_mem_addr.write(1);
	y_mem_addr.write(1);
	zero.write(0);
	one.write(1);

	network2x2.clk(clk); network2x2.rst(rst);
	network2x2.x0y0din(x0y0din);
	network2x2.x0y0dout(x0y0dout);
	network2x2.x0y0req_net(x0y0req_net);
	network2x2.x0y0ack_net(x0y0ack_net);
	network2x2.x0y0ack_dp(x0y0ack_dp);
	network2x2.x0y0req_dp(x0y0req_dp);
	network2x2.x0y1din(x0y1din);
	network2x2.x0y1dout(x0y1dout);
	network2x2.x0y1req_net(x0y1req_net);
	network2x2.x0y1ack_net(x0y1ack_net);
	network2x2.x0y1ack_dp(x0y1ack_dp);
	network2x2.x0y1req_dp(x0y1req_dp);
	network2x2.x1y0din(x1y0din);
	network2x2.x1y0dout(x1y0dout);
	network2x2.x1y0req_net(x1y0req_net);
	network2x2.x1y0ack_net(x1y0ack_net);
	network2x2.x1y0ack_dp(x1y0ack_dp);
	network2x2.x1y0req_dp(x1y0req_dp);
	network2x2.x1y1din(x1y1din);
	network2x2.x1y1dout(x1y1dout);
	network2x2.x1y1req_net(x1y1req_net);
	network2x2.x1y1ack_net(x1y1ack_net);
	network2x2.x1y1ack_dp(x1y1ack_dp);
	network2x2.x1y1req_dp(x1y1req_dp);
	dp_x0y0.clock(clk); dp_x0y0.reset(rst); dp_x0y0.enable(en);
	dp_x0y1.clock(clk); dp_x0y1.reset(rst); dp_x0y1.enable(en);
	dp_x1y0.clock(clk); dp_x1y0.reset(rst); dp_x1y0.enable(en);
	dp_x1y1.clock(clk); dp_x1y1.reset(rst); //dp_x1y1.enable(en);
	dp_x0y0.data_in(x0y0dout);
	dp_x0y0.data_out(x0y0din);
	dp_x0y0.req_out(x0y0req_net);
	dp_x0y0.ack_in(x0y0ack_net);
	dp_x0y0.ack_out(x0y0ack_dp);
	dp_x0y0.req_in(x0y0req_dp);
	dp_x0y0.x_mem_addr(x_mem_addr);
	dp_x0y0.y_mem_addr(y_mem_addr);
	dp_x0y0.my_xaddr(zero);
	dp_x0y0.my_yaddr(zero);
	dp_x0y0.xdimension(xdimension);
	dp_x0y0.ydimension(ydimension);

	dp_x0y1.data_in(x0y1dout);
	dp_x0y1.data_out(x0y1din);
	dp_x0y1.req_out(x0y1req_net);
	dp_x0y1.ack_in(x0y1ack_net);
	dp_x0y1.ack_out(x0y1ack_dp);
	dp_x0y1.req_in(x0y1req_dp);
	dp_x0y1.x_mem_addr(x_mem_addr);
	dp_x0y1.y_mem_addr(y_mem_addr);
	dp_x0y1.my_xaddr(zero);
	dp_x0y1.my_yaddr(one);
	dp_x0y1.xdimension(xdimension);
	dp_x0y1.ydimension(ydimension);

	dp_x1y0.data_in(x1y0dout);
	dp_x1y0.data_out(x1y0din);
	dp_x1y0.req_out(x1y0req_net);
	dp_x1y0.ack_in(x1y0ack_net);
	dp_x1y0.ack_out(x1y0ack_dp);
	dp_x1y0.req_in(x1y0req_dp);
	dp_x1y0.x_mem_addr(x_mem_addr);
	dp_x1y0.y_mem_addr(y_mem_addr);
	dp_x1y0.my_xaddr(one);
	dp_x1y0.my_yaddr(zero);
	dp_x1y0.xdimension(xdimension);
	dp_x1y0.ydimension(ydimension);

		
	dp_x1y1.data_in(x1y1dout);
	dp_x1y1.data_out(x1y1din);
	dp_x1y1.req_out(x1y1req_net);
	dp_x1y1.ack_in(x1y1ack_net);
	dp_x1y1.ack_out(x1y1ack_dp);
	dp_x1y1.req_in(x1y1req_dp);
	
	dp_x1y1.xdimension(xdimension);
	dp_x1y1.ydimension(ydimension);

	sc_signal<sc_uint<32> > dp_x0y0_ramADDR;
	sc_signal<sc_int<32> > dp_x0y0_ramDI;
	sc_signal<sc_int<32> > dp_x0y0_ramDO;
	sc_signal<bool> dp_x0y0_ramEN;
	sc_signal<bool> dp_x0y0_ramCLK;
	sc_signal<bool> dp_x0y0_ramWE;
	sc_signal<bool> dp_x0y0_ramRST;
	sc_signal<sc_uint<32> > dp_x0y0_romADDR;
	sc_signal<sc_int<32> > dp_x0y0_romDI;
	sc_signal<sc_int<32> > dp_x0y0_romDO;
	sc_signal<bool> dp_x0y0_romEN;
	sc_signal<bool> dp_x0y0_romCLK;
	sc_signal<bool> dp_x0y0_romWE;
	sc_signal<bool> dp_x0y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y0_xDO;
	sc_signal< sc_uint<32> > dp_x0y0_xADDR;
	sc_signal< bool > dp_x0y0_xCLK, dp_x0y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y1_ramADDR;
	sc_signal<sc_int<32> > dp_x0y1_ramDI;
	sc_signal<sc_int<32> > dp_x0y1_ramDO;
	sc_signal<bool> dp_x0y1_ramEN;
	sc_signal<bool> dp_x0y1_ramCLK;
	sc_signal<bool> dp_x0y1_ramWE;
	sc_signal<bool> dp_x0y1_ramRST;
	sc_signal<sc_uint<32> > dp_x0y1_romADDR;
	sc_signal<sc_int<32> > dp_x0y1_romDI;
	sc_signal<sc_int<32> > dp_x0y1_romDO;
	sc_signal<bool> dp_x0y1_romEN;
	sc_signal<bool> dp_x0y1_romCLK;
	sc_signal<bool> dp_x0y1_romWE;
	sc_signal<bool> dp_x0y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y1_xDO;
	sc_signal< sc_uint<32> > dp_x0y1_xADDR;
	sc_signal< bool > dp_x0y1_xCLK, dp_x0y1_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y0_ramADDR;
	sc_signal<sc_int<32> > dp_x1y0_ramDI;
	sc_signal<sc_int<32> > dp_x1y0_ramDO;
	sc_signal<bool> dp_x1y0_ramEN;
	sc_signal<bool> dp_x1y0_ramCLK;
	sc_signal<bool> dp_x1y0_ramWE;
	sc_signal<bool> dp_x1y0_ramRST;
	sc_signal<sc_uint<32> > dp_x1y0_romADDR;
	sc_signal<sc_int<32> > dp_x1y0_romDI;
	sc_signal<sc_int<32> > dp_x1y0_romDO;
	sc_signal<bool> dp_x1y0_romEN;
	sc_signal<bool> dp_x1y0_romCLK;
	sc_signal<bool> dp_x1y0_romWE;
	sc_signal<bool> dp_x1y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y0_xDO;
	sc_signal< sc_uint<32> > dp_x1y0_xADDR;
	sc_signal< bool > dp_x1y0_xCLK, dp_x1y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y1_ramADDR;
	sc_signal<sc_int<32> > dp_x1y1_ramDI;
	sc_signal<sc_int<32> > dp_x1y1_ramDO;
	sc_signal<bool> dp_x1y1_ramEN;
	sc_signal<bool> dp_x1y1_ramCLK;
	sc_signal<bool> dp_x1y1_ramWE;
	sc_signal<bool> dp_x1y1_ramRST;
	sc_signal<sc_uint<32> > dp_x1y1_romADDR;
	sc_signal<sc_int<32> > dp_x1y1_romDI;
	sc_signal<sc_int<32> > dp_x1y1_romDO;
	sc_signal<bool> dp_x1y1_romEN;
	sc_signal<bool> dp_x1y1_romCLK;
	sc_signal<bool> dp_x1y1_romWE;
	sc_signal<bool> dp_x1y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y1_xDO;
	sc_signal< sc_uint<32> > dp_x1y1_xADDR;
	sc_signal< bool > dp_x1y1_xCLK, dp_x1y1_xWE;
#endif

	dp_x0y0.ramADDR(dp_x0y0_ramADDR);
	dp_x0y0.ramDI(dp_x0y0_ramDI);
	dp_x0y0.ramDO(dp_x0y0_ramDO);
	dp_x0y0.ramEN(dp_x0y0_ramEN);
	dp_x0y0.ramCLK(dp_x0y0_ramCLK);
	dp_x0y0.ramWE(dp_x0y0_ramWE);
	dp_x0y0.ramRST(dp_x0y0_ramRST);
	dp_x0y0.romADDR(dp_x0y0_romADDR);
	dp_x0y0.romDI(dp_x0y0_romDI);
	dp_x0y0.romDO(dp_x0y0_romDO);
	dp_x0y0.romEN(dp_x0y0_romEN);
	dp_x0y0.romCLK(dp_x0y0_romCLK);
	dp_x0y0.romWE(dp_x0y0_romWE);