translator_mem.cpp

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   translator_mem.cpp
 *
 *  Author          :   Jose Prats - [e-mail]
 *
 *  Date            :
 *
 *  Function        :   Translator in memory node
 *
 */

#include "translator_mem.h"

/*void TRANSLATOR_MEM::rd_wr_buffer()
{
  if( rst.read() == true )
    rd_wr_buff = false;
  else
    rd_wr_buff = rd_wr.read();
}   */

void TRANSLATOR_MEM::translator_process()
{
  rd_wr_tmp.write(rd_wr);

  // Slect the proper signals to send to NI depending on the "remote select"
  //trans_dev_w.write(int_dev_waddr.read() );
  trans_dev_wdata.write(int_dev_wdata.read() );
  trans_dev_waddr.write(int_dev_waddr.read() );
  trans_dev_send_eop.write(int_dev_send_eop.read() );
  
  if (send_rdy.read() == true)
    {
    is_send_rdy.write(is_send_rdy.read() ? false : true);
    }
 
 
}

void TRANSLATOR_MEM::translatorFSM_receive() {
  
  
  if (rst.read() == true) {
    rcv_next_state = rcv_idle;
    //rem_mem_r.write(sc_bv<2>(0));
    rem_mem_w.write(sc_bv<2>(0));
    trans_dev_r.write(true);    
    rd_wr_buff.write(false);
    do_send.write(false);

  }
  else {
    switch(rcv_current_state) {
      case rcv_idle:                     
        do_send.write(false);
	//rem_mem_r.write(sc_bv<2>(0));
	rem_mem_w.write(sc_bv<2>(0));
	
	if (rd_wr.read() == 1)		//activate the RD/WR buffer if we're receiving a RD
          {
          rd_wr_buff = rd_wr.read();
          }
	  
        if (data_rdy.read() == 1) 	//we have to manage the data in different way if we receive a RD or a WR
	  {	  
          if (rd_wr_buff)
            {
            rcv_next_state = get_addr;
            buffer_rel_addr = reg_data_out.read();
            }
          else
            {
            rcv_next_state = write_addr;
            buffer_addr = reg_data_out.read();
            }
	  }
        else
	  {
          rcv_next_state = rcv_idle;
          //rem_mem_r.write(sc_bv<2>(0));
          rem_mem_w.write(sc_bv<2>(0));
	  }
        break;

      case get_addr:	
	
        if (data_rdy.read() == 1)
	  {
          rcv_next_state = write_addr;	//get the first packet, is the address to be read
          buffer_addr = reg_data_out.read();	  
	  }
        else
	  {
          rcv_next_state = get_addr;
	  }
        break;

      case write_addr:        
	rem_mem_addr.write(buffer_addr);
        if(rd_wr_buff)
          {
          rcv_next_state = mem_access;	//access to the memory if it is a RD	  
          }
        else
          {    
          rcv_next_state = write_data;	//write the data to be stored if it is a WR
          }
        break;

      case write_data:
        if (data_rdy.read() == 1)	//waiting for receive the data
	  {
          rcv_next_state = mem_access;
          buffer_data = reg_data_out.read();
          rem_mem_din.write(buffer_data); 	  
	  }
        else
	  {
          rcv_next_state = write_data;
	  }
        break;

      case mem_access:
	
        if (rd_wr_buff)	//It is a RD
          {
	  //rem_mem_r.write(10);
          //rem_mem_w.write(sc_bv<2>(0));          
	  do_send.write(true);	  
	  //rd_wr_buff = false;
	  rcv_next_state = rd_wr_buff_down;
          }
        else  //It is a WR
          {
          //rem_mem_r.write(sc_bv<2>(0));
          rem_mem_w.write(sc_bv<2>(10)); 
	  rcv_next_state = rcv_idle;         
          }
	
        break;
     
      case rd_wr_buff_down:
	
	  rd_wr_buff = false;
	  rcv_next_state = rcv_idle;         
          
        break;
      /*case do_send_data:
        rem_mem_r.write(0);

        x_mem_rel_addr = buffer_rel_addr.range(31,24);
        y_mem_rel_addr = buffer_rel_addr.range(23,16);

        xdimension_int = xdimension.read();
        ydimension_int = ydimension.read();

        //send_rel_xaddr.write( (x_mem_rel_addr == sc_int<8>(0)) ? sc_int<8>(0) : (xdimension_int - x_mem_rel_addr) );
        if (x_mem_rel_addr == sc_int<8>(0))
          {
          send_rel_xaddr =  sc_int<8>(0);
          }
        else
          {
          send_rel_xaddr = (xdimension_int - x_mem_rel_addr);
          }

        //send_rel_yaddr.write( (y_mem_rel_addr == sc_int<8>(0)) ? sc_int<8>(0) : (ydimension_int - y_mem_rel_addr) );
        if (y_mem_rel_addr == sc_int<8>(0))
          {
          send_rel_yaddr =  sc_int<8>(0);
          }
        else
          {
          send_rel_yaddr = (ydimension_int - y_mem_rel_addr);
          }

        send_rel_xaddr_bit = send_rel_xaddr;
        send_rel_yaddr_bit = send_rel_yaddr;

        send_mem_CWeop.range(31,8) = (control_CWeop_store,send_rel_xaddr_bit);
        send_mem_CWeop.range(7,0) = send_rel_yaddr_bit;

        rem_mem_dout_buff = rem_mem_dout.read();

        trans_dev_din.write(rem_mem_dout_buff.read());

        int_dev_wdata.write(true);
        int_dev_waddr.write(false);
        int_dev_send_eop.write(false);
	

        rcv_next_state = keep_data_on_bus;
        break;

      case keep_data_on_bus:
        trans_dev_din.write(rem_mem_dout_buff.read());

        rcv_next_state = do_send_CW;
        break;

      case do_send_CW:
      
        if (rd_wr.read() == 1)
          {
          rd_wr_buff = rd_wr.read();
          }
        
	trans_dev_din.write(send_mem_CWeop);
        int_dev_wdata.write(false);
        int_dev_waddr.write(true);
        //int_dev_send_eop.write(true);	
	
	if (!send_rdy)
          {
	  rcv_next_state = do_send_CW;
          }
        else
          {
	  trans_dev_w.write(true);
	  int_dev_send_eop.write(true);
	  rcv_next_state = rcv_finish;
	  }  
        break;	    

      case rcv_finish:  
        rd_wr_buff = false;
	trans_dev_w.write(false);
        int_dev_send_eop.write(false);
	rem_mem_w.write(sc_bv<2>(0));
	     
        if (!send_rdy)
          {
	  rcv_next_state = rcv_finish;	  
          }
        else
          {             
          rcv_next_state = rcv_idle;
          }   

        break;*/
    }
    
  }
}



// state update of the receive FSM
void TRANSLATOR_MEM::rcv_change_state()
{
  if( rst.read() ){
    rcv_current_state = rcv_idle;
  }
  else{
    rcv_current_state = rcv_next_state;

  }
}



void TRANSLATOR_MEM::translatorFSM_send() {
  
if (rst.read() == true) {
    send_next_state = send_idle;
    trans_dev_w.write(false);
    int_dev_send_eop.write(false);    
    rem_mem_r.write(sc_bv<2>(0));
  }
  
else {
    switch(send_current_state) {
        case send_idle: 
	  
	  trans_dev_w.write(false);
          int_dev_send_eop.write(false);
	  
	  if (do_send.read() == 1)
	    {
	    rem_mem_r.write(sc_bv<2>(10));
            //rem_mem_w.write(sc_bv<2>(0));
	    send_next_state = do_send_data;
	    }
	  else
	    {	    
	    send_next_state = send_idle;
	    rem_mem_r.write(sc_bv<2>(0));
	    }       
        
        break;
	
	case do_send_data: 
	
	  //rem_mem_r.write(sc_bv<2>(0));  
                    
          x_mem_rel_addr = buffer_rel_addr.range(31,24);
          y_mem_rel_addr = buffer_rel_addr.range(23,16);

          xdimension_int = xdimension.read();
          ydimension_int = ydimension.read();

          //send_rel_xaddr.write( (x_mem_rel_addr == sc_int<8>(0)) ? sc_int<8>(0) : (xdimension_int - x_mem_rel_addr) );
          if (x_mem_rel_addr == sc_int<8>(0))
            {
            send_rel_xaddr =  sc_int<8>(0);
            }
          else
            {
            send_rel_xaddr = (xdimension_int - x_mem_rel_addr);
            }

          //send_rel_yaddr.write( (y_mem_rel_addr == sc_int<8>(0)) ? sc_int<8>(0) : (ydimension_int - y_mem_rel_addr) );
          if (y_mem_rel_addr == sc_int<8>(0))
            {
            send_rel_yaddr =  sc_int<8>(0);
            }
          else
            {
            send_rel_yaddr = (ydimension_int - y_mem_rel_addr);
            }

          send_rel_xaddr_bit = send_rel_xaddr;
          send_rel_yaddr_bit = send_rel_yaddr;

          send_mem_CWeop.range(31,8) = (control_CWeop_store,send_rel_xaddr_bit);
          send_mem_CWeop.range(7,0) = send_rel_yaddr_bit;

          /*rem_mem_dout_buff = rem_mem_dout.read();

          trans_dev_din.write(rem_mem_dout_buff.read());*/ 

          //int_dev_wdata.write(true);
          //int_dev_waddr.write(false);
          //int_dev_send_eop.write(false);

          send_next_state = keep_data_on_bus;
          break;
	  
      case keep_data_on_bus:
        rem_mem_r.write(sc_bv<2>(0));
	
	rem_mem_dout_buff = rem_mem_dout.read();
        trans_dev_din.write(rem_mem_dout_buff.read());
	
        int_dev_wdata.write(true);
        int_dev_waddr.write(false);
        trans_dev_din.write(rem_mem_dout_buff.read());
        send_next_state = do_send_CW;
        break;

      case do_send_CW:
        
	trans_dev_din.write(send_mem_CWeop);
        int_dev_wdata.write(false);
        int_dev_waddr.write(true);        
	
	if (!send_rdy)
          {
	  send_next_state = do_send_CW;
          }
        else
          {
	  /*trans_dev_w.write(true);
	  int_dev_send_eop.write(true);
	  send_next_state = send_idle;*/
	  
	  send_next_state = wait_for_send;
	  }  
        break;
      
      case wait_for_send:
	send_next_state = send_finish;
	 
        break;

      case send_finish:
        trans_dev_w.write(true);
	int_dev_send_eop.write(true);
	send_next_state = send_idle;
	
	break;
    
        }
     } 
}



// state update of the receive FSM
void TRANSLATOR_MEM::send_change_state()
{
  if( rst.read() ){
    send_current_state = send_idle;
  }
  else{
    send_current_state = send_next_state;

  }
}