main_benif.cpp

改进的基于6个mips核的NOC网络

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   
 *
 */
 

// undefine NOVCD to enable tracing of mMIPS internal signals
#define NOVCD 1

#include "mips_trace.h"
#include "benif.h"

// 
//  MAIN
//

// a module to write to a bidirectional resolved signal
SC_MODULE(W){
  sc_in< sc_lv<32> > nrvi;
  sc_inout_rv<32> rv;
  SC_CTOR(W){
	SC_METHOD(w);
	sensitive << nrvi;	
  }
  void w(){
	rv.write(nrvi.read());
  }
};

// a module to read from bidirectional resolved signal
SC_MODULE(R){
  sc_in_rv<32> rv;
  sc_out< sc_lv<32> > nrvo;
  SC_CTOR(R){
	SC_METHOD(r);
	sensitive << rv;
  }
  void r(){
	nrvo.write(rv.read());
  }
};

int sc_main(int argc, char *argv[])
{
  char stbuf[1024];
  
  // the mMIPS with communication hardware
  BENIF benif("benif");
  
  sc_signal< bool > MIPSCLK;
  sc_signal< bool > IFCLK;
  sc_signal< bool > WRITE_STROBE;
  sc_signal< bool > READ_STROBE;
  sc_signal< bool > DMA_ENABLE;
  sc_signal< bool > DMA_DIRECTION;
  sc_signal< bool > DMA_RDY;
  sc_signal< bool > DMA_DATA_AVAILABLE;
  sc_signal< bool > RST;
  sc_signal< bool > SYNC_RESET;
  sc_signal< bool > DMA_RESET;
  sc_signal< sc_uint<31> > ADDRESS;
  sc_signal< sc_uint<32> > COUNT;
  sc_signal< sc_uint<4> > DMA_SEL;
  sc_signal< bool > DMA_WEN;
  sc_signal< bool > DMA_REN;
  sc_signal< bool > INT;
  sc_signal< sc_bv<4> > LEDS;

  benif.MIPSCLK(MIPSCLK);
  benif.IFCLK(IFCLK);
  benif.WRITE_STROBE(WRITE_STROBE);
  benif.READ_STROBE(READ_STROBE);
  benif.DMA_ENABLE(DMA_ENABLE);
  benif.DMA_DIRECTION(DMA_DIRECTION);
  benif.DMA_RDY(DMA_RDY);
  benif.DMA_DATA_AVAILABLE(DMA_DATA_AVAILABLE);
  benif.RST(RST);
  benif.SYNC_RESET(SYNC_RESET);
  benif.DMA_RESET(DMA_RESET);
  benif.ADDRESS(ADDRESS);
  benif.COUNT(COUNT);
  benif.DMA_SEL(DMA_SEL);
  benif.DMA_WEN(DMA_WEN);
  benif.DMA_REN(DMA_REN);
  benif.INT(INT);
  benif.LEDS(LEDS);

  
  // bidirectional, resolved signals are connected to buses 
  // by R and W modules
  sc_signal_rv<32> DATA, DMA_DATA;
  sc_signal< sc_lv<32> > DATAi, DATAo, DMA_DATAi, DMA_DATAo;
  
  R rd("rd"), rdm("rdm");
  W wd("wd"), wdm("wdm");
  
  rd.rv(DATA); 
  rd.nrvo(DATAo);
  wd.rv(DATA);
  wd.nrvi(DATAi);
  
  rdm.rv(DMA_DATA); 
  rdm.nrvo(DMA_DATAo);
  wdm.rv(DMA_DATA);
  wdm.nrvi(DMA_DATAi);
  
  benif.DATA(DATA);
  benif.DMA_DATA(DMA_DATA);
  
  
#ifndef NOVCD
  sc_trace_file *tf;
  tf = sc_create_vcd_trace_file("mips");
  trace_mips(tf, &benif.mmips, "mips");
#endif

  benif.mmips->dmem->mem_init("mips_ram.bin");
  benif.mmips->imem->mem_init("mips_rom.bin");
  benif.mmips->dmem->mem_dump("mips_ram.0.dump");
  benif.mmips->imem->mem_dump("mips_rom.0.dump");
  /*********************************************************************************
 	Start simulation
  *********************************************************************************/

  DATAi = 0; DMA_DATAi = 0;

  sc_initialize();

  
  /*
   *	Simulate program execution
   */
  int max_time = 0;
  if (argc == 2) max_time = atoi(argv[1]);
  if (max_time == 0) max_time = 500;
  int period = 10, sim_time=0;

  // reset the system
  RST = 1;
  // two ticks if I/F clock, 1 tick of MIPS clock
  IFCLK = 0; MIPSCLK = 0; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
  IFCLK = 0; MIPSCLK = 1; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
  RST = 0;

  // enable the processor (write to register 4)
  IFCLK = 0; MIPSCLK = 0; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
  ADDRESS = 4; DATAi = 0xffffffff; WRITE_STROBE = 1;  
  IFCLK = 0; MIPSCLK = 1; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
  WRITE_STROBE = 0; DATAi = sc_lv<32>(SC_LOGIC_Z);


  unsigned pc;
  
  // run until simulation time or pc==16 
  while( max_time < 0 || sim_time < (unsigned)max_time )
	{
      IFCLK = 0; MIPSCLK = 0; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
      IFCLK = 0; MIPSCLK = 1; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
	  sim_time += 2*period;
	  
	  pc = sc_uint<32>(benif.pc.read());
	  if( pc == 0x10 ) { cout << "END: " << sim_time/period << " cycles " << sc_time_stamp() << endl; break;}
	}
	

  // disable the processor
  IFCLK = 0; MIPSCLK = 0; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
  ADDRESS = 4; DATAi = 0; WRITE_STROBE = 1;  
  IFCLK = 0; MIPSCLK = 1; sc_cycle(period/2); IFCLK = 1; sc_cycle(period/2);
  WRITE_STROBE = 0; DATAi = sc_lv<32>(SC_LOGIC_Z);


  benif.mmips->dmem->mem_dump("mips_ram.dump");
  
#ifndef NOVCD
  sc_close_vcd_trace_file(tf);
#endif
  return 0;
}