netmips.h

改进的基于6个mips核的NOC网络

#ifndef NETMIPS_H_DEFINED
#define NETMIPS_H_DEFINED

#include "mmips.h"
#include "netif_b.h"

#ifdef CACHE
#include "cache_mips.h"
#endif

SC_MODULE(NETmMIPS)
{
  
#ifdef CACHE
  CACHE_MIPS *mips;
#else
  mMIPS *mips;
#endif
  
  NETWORK_INTERFACE *netif;
  

  sc_in<bool> clock;
  sc_in<bool> enable;
  sc_in<bool> reset;

  // network interface
  sc_in< sc_bv<FLIT_LEN> > data_in;
  sc_in< bool > req_in, ack_in;

  sc_out< sc_bv<FLIT_LEN> > data_out;
  sc_out< bool > req_out, ack_out;


  // mips interface
  sc_signal< sc_bv<DWORD> > dout;
  sc_signal< sc_bv<DWORD> > din;
  sc_signal< bool > r, w;
  sc_signal< bool > rdyr, rdyw;
  sc_signal< bool > wdata, waddr;
  sc_signal< bool > send_eop, rcv_eop;
  sc_signal< bool > rd_wr;  //<---------------cambios JPO!!
  
  sc_in < sc_int<8> > x_mem_addr;  //<-------- cambios JPO!!
  sc_in < sc_int<8> > y_mem_addr;
  sc_in < sc_int<8> > my_xaddr;
  sc_in < sc_int<8> > my_yaddr;
  sc_in < sc_int<8> > xdimension;
  sc_in < sc_int<8> > ydimension;

  sc_out< sc_bv<DWORD> >    bus_pc;

  sc_out<sc_int<32> > ramDO;
  sc_in<sc_uint<32> > ramADDR;
  sc_in<sc_int<32> > ramDI;
  sc_in<bool> ramEN;
  sc_in<bool> ramCLK;
  sc_in<bool> ramWE;
  sc_in<bool> ramRST;

  sc_out<sc_int<32> > romDO;
  sc_in<sc_uint<32> > romADDR;
  sc_in<sc_int<32> > romDI;
  sc_in<bool> romEN;
  sc_in<bool> romCLK;
  sc_in<bool> romWE;
  sc_in<bool> romRST;
  

#ifdef USEXRAM
  sc_out< sc_int<32> > xDO;
  sc_in< sc_uint<32> > xADDR;
  sc_in< bool > xCLK, xWE;
#endif
  
  SC_CTOR(NETmMIPS)
	{
#ifdef CACHE
	  mips = new CACHE_MIPS("mips");
#else	  
	  mips = new mMIPS("mips");
#endif
	  
	  netif = new NETWORK_INTERFACE("netif");
	  	  
	  mips->clock(clock);
	  mips->enable(enable);
	  mips->reset(reset);
	  
	  mips->dev_dout(dout);
	  mips->dev_din(din);
	  mips->dev_r(r);
	  mips->dev_w(w);
	  mips->dev_rdyr(rdyr);
	  mips->dev_rdyw(rdyw);
	  mips->dev_wdata(wdata);
	  mips->dev_waddr(waddr);
	  mips->dev_send_eop(send_eop);
	  mips->dev_rcv_eop(rcv_eop);
	  
	  mips->x_mem_addr(x_mem_addr);  //<-------- cambios JPO!!
	  mips->y_mem_addr(y_mem_addr);
	  mips->my_xaddr(my_xaddr);
	  mips->my_yaddr(my_yaddr);
	  mips->xdimension(xdimension);
	  mips->ydimension(ydimension);
	  

	  netif->clk(clock); netif->rst(reset);
	  netif->data_in(data_in);
	  netif->data_out(data_out);
	  netif->req_in(req_in);
	  netif->ack_in(ack_in);
	  netif->req_out(req_out);
	  netif->ack_out(ack_out);

	  netif->reg_data_in(dout);
	  netif->write_data(wdata);
	  netif->write_addr(waddr);
	  netif->send(w);
	  netif->read(r);
	  netif->reg_data_out(din);
	  netif->data_rdy(rdyr);
	  netif->send_rdy(rdyw);
	  netif->packet_end( send_eop );
	  netif->rcv_packet_end( rcv_eop );
	  netif->rd_wr(rd_wr);  //<--------- cambios JPO!!
	  
	  mips->bus_pc(bus_pc);
  
	  mips->ramDO(ramDO);
	  mips->ramADDR(ramADDR);
	  mips->ramDI(ramDI);
	  mips->ramEN(ramEN);
	  mips->ramCLK(ramCLK);
	  mips->ramWE(ramWE);
	  mips->ramRST(ramRST);

	  mips->romDO(romDO);
	  mips->romADDR(romADDR);
	  mips->romDI(romDI);
	  mips->romEN(romEN);
	  mips->romCLK(romCLK);
	  mips->romWE(romWE);
	  mips->romRST(romRST);

#ifdef USEXRAM
	  mips->xDO(xDO);
	  mips->xADDR(xADDR);
	  mips->xCLK(xCLK);
	  mips->xWE(xWE);
#endif
	}
};

#endif