fifocnt4.vhd

来自「基于4个mips核的noc设计」· VHDL 代码 · 共 82 行

--------------------------------------------------------------------------
--  Design: FIFOCNT4 
--  File:   $Id: fifocnt4.vhd,v 1.1 2003/10/31 11:45:09 aslusarc Exp $
--
--  This is a special counter for FIFO Applications
--  When the 'direction' is to count down, the read enable does not
--  need to be asserted, this is so that the counter can be backed up on
--  a single signal
--
--  Copyright (c) 1998 Nallatech Ltd.  All rights reserved.
----------------------------------------------------------------------------							

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
--library SYNOPSYS;
--use SYNOPSYS.std_logic_unsigned.all;
--use SYNOPSYS.std_logic_arith.all;


entity FIFOCNT4 is
	port(
		CLK 	: in std_logic;
		GSR_RST	: in std_logic;
		SW_RST	: in std_logic;
		CE 	: in std_logic;
		DIR 	: in std_logic;
		Q	: out std_logic_vector(3 downto 0)
	);
	
end FIFOCNT4;


architecture FIFOCNT4_arch of FIFOCNT4 is

signal COUNT : integer range 0 to 15;
signal SYNCRST : std_logic;

begin

	-- Ensure that reset signal is synced to the clk in this domain
	DOSYNCRST : process(CLK,GSR_RST)
	begin
		if GSR_RST='1' then
			SYNCRST <= '1';
		elsif CLK'event and CLK='1' then
			SYNCRST <= SW_RST;
		end if;
	end process DOSYNCRST;
	
	-- Perform the counting
	Q <= CONV_STD_LOGIC_VECTOR(COUNT,4);
	
	DOCOUNT : process (CLK, GSR_RST, SYNCRST, CE,DIR)
	begin
		if GSR_RST='1' then
			COUNT <= 0;
		elsif CLK='1' and CLK'event then
			if SYNCRST='1' then
				COUNT <= 0;
			elsif CE='1' or DIR='0' then
				if DIR='1' then  
--					if COUNT=15 then
--						COUNT <= 0;
--					else	 
						COUNT <= COUNT + 1;
--					end if;	
				else
--					if COUNT=0 then
--						COUNT <= 15;
--					else	
						COUNT <= COUNT - 1;
--					end if;	
				end if;
			end if;
		end if;
	end process;

end FIFOCNT4_arch;