minimips.c

基于4个mips核的noc设计

#define INTTMP 0x0100ff00	/* 8-15, 24 */
#define INTVAR 0x00ff0000	/* 16-23 */
#define INTRET 0x00000004	/* 2 */

#define readsreg(p) \
        (generic((p)->op)==INDIR && (p)->kids[0]->op==VREG+P)
#define setsrc(d) ((d) && (d)->x.regnode && \
        (d)->x.regnode->set == src->x.regnode->set && \
        (d)->x.regnode->mask&src->x.regnode->mask)

#define relink(a, b) ((b)->x.prev = (a), (a)->x.next = (b))

#include "c.h"
#define NODEPTR_TYPE Node
#define OP_LABEL(p) ((p)->op)
#define LEFT_CHILD(p) ((p)->kids[0])
#define RIGHT_CHILD(p) ((p)->kids[1])
#define STATE_LABEL(p) ((p)->x.state)
static void address (Symbol, Symbol, long);
static void blkfetch (int, int, int, int);
static void blkloop (int, int, int, int, int, int[]);
static void blkstore (int, int, int, int);
static void defaddress (Symbol);
static void defconst (int, int, Value);
static void defstring (int, char *);
static void defsymbol (Symbol);
static void doarg (Node);
static void emit2 (Node);
static void export (Symbol);
static void clobber (Node);
static void function (Symbol, Symbol[], Symbol[], int);
static void global (Symbol);
static void import (Symbol);
static void local (Symbol);
static void progbeg (int, char **);
static void progend (void);
static void segment (int);
static void space (int);
static void target (Node);
static int mulops_calls(int op);
static int bitcount (unsigned);
static Symbol argreg (int, int, int, int, int);

static Symbol ireg[32];
static Symbol iregw;
static int tmpregs[] = { 3, 9, 10, 30 };
static Symbol blkreg;

static int cseg;
/*
generated at Tue Dec 18 12:36:59 2007
by $Id: lburg.c,v 2.8 1997/10/30 23:41:10 drh Exp $
*/
static void _kids(NODEPTR_TYPE, int, NODEPTR_TYPE[]);
static void _label(NODEPTR_TYPE);
static int _rule(void*, int);

#define _stmt_NT 1
#define _reg_NT 2
#define _con_NT 3
#define _acon_NT 4
#define _addr_NT 5
#define _rc_NT 6
#define _ar_NT 7
#define _magic_addr_NT 8

static char *_ntname[] = {
	0,
	"stmt",
	"reg",
	"con",
	"acon",
	"addr",
	"rc",
	"ar",
	"magic_addr",
	0
};

struct _state {
	short cost[9];
	struct {
		unsigned int _stmt:6;
		unsigned int _reg:7;
		unsigned int _con:3;
		unsigned int _acon:2;
		unsigned int _addr:3;
		unsigned int _rc:2;
		unsigned int _ar:2;
		unsigned int _magic_addr:1;
	} rule;
};

static short _nts_0[] = { 0 };
static short _nts_1[] = { _reg_NT, 0 };
static short _nts_2[] = { _con_NT, 0 };
static short _nts_3[] = { _reg_NT, _acon_NT, 0 };
static short _nts_4[] = { _acon_NT, 0 };
static short _nts_5[] = { _addr_NT, 0 };
static short _nts_6[] = { _addr_NT, _reg_NT, 0 };
static short _nts_7[] = { _reg_NT, _reg_NT, 0 };
static short _nts_8[] = { _reg_NT, _rc_NT, 0 };
static short _nts_9[] = { _ar_NT, 0 };
static short _nts_10[] = { _reg_NT, _reg_NT, _magic_addr_NT, 0 };
static short _nts_11[] = { _reg_NT, _reg_NT, _reg_NT, _magic_addr_NT, 0 };

static short *_nts[] = {
	0,	/* 0 */
	_nts_0,	/* 1 */
	_nts_0,	/* 2 */
	_nts_0,	/* 3 */
	_nts_0,	/* 4 */
	_nts_0,	/* 5 */
	_nts_0,	/* 6 */
	_nts_1,	/* 7 */
	_nts_1,	/* 8 */
	_nts_1,	/* 9 */
	_nts_1,	/* 10 */
	_nts_1,	/* 11 */
	_nts_1,	/* 12 */
	_nts_0,	/* 13 */
	_nts_0,	/* 14 */
	_nts_0,	/* 15 */
	_nts_0,	/* 16 */
	_nts_0,	/* 17 */
	_nts_1,	/* 18 */
	_nts_2,	/* 19 */
	_nts_0,	/* 20 */
	_nts_3,	/* 21 */
	_nts_3,	/* 22 */
	_nts_3,	/* 23 */
	_nts_4,	/* 24 */
	_nts_1,	/* 25 */
	_nts_0,	/* 26 */
	_nts_0,	/* 27 */
	_nts_5,	/* 28 */
	_nts_0,	/* 29 */
	_nts_0,	/* 30 */
	_nts_0,	/* 31 */
	_nts_0,	/* 32 */
	_nts_0,	/* 33 */
	_nts_0,	/* 34 */
	_nts_6,	/* 35 */
	_nts_6,	/* 36 */
	_nts_6,	/* 37 */
	_nts_6,	/* 38 */
	_nts_6,	/* 39 */
	_nts_5,	/* 40 */
	_nts_5,	/* 41 */
	_nts_5,	/* 42 */
	_nts_5,	/* 43 */
	_nts_5,	/* 44 */
	_nts_5,	/* 45 */
	_nts_5,	/* 46 */
	_nts_5,	/* 47 */
	_nts_5,	/* 48 */
	_nts_6,	/* 49 */
	_nts_7,	/* 50 */
	_nts_7,	/* 51 */
	_nts_7,	/* 52 */
	_nts_7,	/* 53 */
	_nts_7,	/* 54 */
	_nts_7,	/* 55 */
	_nts_2,	/* 56 */
	_nts_1,	/* 57 */
	_nts_8,	/* 58 */
	_nts_8,	/* 59 */
	_nts_8,	/* 60 */
	_nts_8,	/* 61 */
	_nts_8,	/* 62 */
	_nts_8,	/* 63 */
	_nts_8,	/* 64 */
	_nts_8,	/* 65 */
	_nts_8,	/* 66 */
	_nts_8,	/* 67 */
	_nts_8,	/* 68 */
	_nts_8,	/* 69 */
	_nts_1,	/* 70 */
	_nts_1,	/* 71 */
	_nts_1,	/* 72 */
	_nts_1,	/* 73 */
	_nts_7,	/* 74 */
	_nts_7,	/* 75 */
	_nts_7,	/* 76 */
	_nts_7,	/* 77 */
	_nts_1,	/* 78 */
	_nts_1,	/* 79 */
	_nts_1,	/* 80 */
	_nts_1,	/* 81 */
	_nts_1,	/* 82 */
	_nts_1,	/* 83 */
	_nts_1,	/* 84 */
	_nts_1,	/* 85 */
	_nts_1,	/* 86 */
	_nts_7,	/* 87 */
	_nts_7,	/* 88 */
	_nts_7,	/* 89 */
	_nts_7,	/* 90 */
	_nts_1,	/* 91 */
	_nts_1,	/* 92 */
	_nts_1,	/* 93 */
	_nts_1,	/* 94 */
	_nts_1,	/* 95 */
	_nts_1,	/* 96 */
	_nts_1,	/* 97 */
	_nts_0,	/* 98 */
	_nts_4,	/* 99 */
	_nts_1,	/* 100 */
	_nts_7,	/* 101 */
	_nts_7,	/* 102 */
	_nts_7,	/* 103 */
	_nts_7,	/* 104 */
	_nts_7,	/* 105 */
	_nts_7,	/* 106 */
	_nts_7,	/* 107 */
	_nts_7,	/* 108 */
	_nts_7,	/* 109 */
	_nts_7,	/* 110 */
	_nts_7,	/* 111 */
	_nts_7,	/* 112 */
	_nts_7,	/* 113 */
	_nts_7,	/* 114 */
	_nts_7,	/* 115 */
	_nts_7,	/* 116 */
	_nts_7,	/* 117 */
	_nts_7,	/* 118 */
	_nts_9,	/* 119 */
	_nts_9,	/* 120 */
	_nts_9,	/* 121 */
	_nts_9,	/* 122 */
	_nts_9,	/* 123 */
	_nts_1,	/* 124 */
	_nts_0,	/* 125 */
	_nts_0,	/* 126 */
	_nts_0,	/* 127 */
	_nts_10,	/* 128 */
	_nts_10,	/* 129 */
	_nts_10,	/* 130 */
	_nts_10,	/* 131 */
	_nts_11,	/* 132 */
	_nts_1,	/* 133 */
	_nts_1,	/* 134 */
	_nts_1,	/* 135 */
	_nts_1,	/* 136 */
	_nts_1,	/* 137 */
	_nts_1,	/* 138 */
	_nts_1,	/* 139 */
	_nts_1,	/* 140 */
	_nts_1,	/* 141 */
	_nts_1,	/* 142 */
	_nts_7,	/* 143 */
};

static char *_templates[] = {
/* 0 */	0,
/* 1 */	"# read register\n",	/* reg: INDIRI1(VREGP) */
/* 2 */	"# read register\n",	/* reg: INDIRU1(VREGP) */
/* 3 */	"# read register\n",	/* reg: INDIRF4(VREGP) */
/* 4 */	"# read register\n",	/* reg: INDIRI4(VREGP) */
/* 5 */	"# read register\n",	/* reg: INDIRP4(VREGP) */
/* 6 */	"# read register\n",	/* reg: INDIRU4(VREGP) */
/* 7 */	"# write register\n",	/* stmt: ASGNI1(VREGP,reg) */
/* 8 */	"# write register\n",	/* stmt: ASGNU1(VREGP,reg) */
/* 9 */	"# write register\n",	/* stmt: ASGNF4(VREGP,reg) */
/* 10 */	"# write register\n",	/* stmt: ASGNI4(VREGP,reg) */
/* 11 */	"# write register\n",	/* stmt: ASGNP4(VREGP,reg) */
/* 12 */	"# write register\n",	/* stmt: ASGNU4(VREGP,reg) */
/* 13 */	"%a",	/* con: CNSTI1 */
/* 14 */	"%a",	/* con: CNSTU1 */
/* 15 */	"%a",	/* con: CNSTI4 */
/* 16 */	"%a",	/* con: CNSTU4 */
/* 17 */	"%a",	/* con: CNSTP4 */
/* 18 */	"",	/* stmt: reg */
/* 19 */	"%0",	/* acon: con */
/* 20 */	"%a",	/* acon: ADDRGP4 */
/* 21 */	"%1($%0)",	/* addr: ADDI4(reg,acon) */
/* 22 */	"%1($%0)",	/* addr: ADDU4(reg,acon) */
/* 23 */	"%1($%0)",	/* addr: ADDP4(reg,acon) */
/* 24 */	"%0",	/* addr: acon */
/* 25 */	"($%0)",	/* addr: reg */
/* 26 */	"%a+%F($sp)",	/* addr: ADDRFP4 */
/* 27 */	"%a+%F($sp)",	/* addr: ADDRLP4 */
/* 28 */	"\tla $%c,%0\n",	/* reg: addr */
/* 29 */	"# reg\n",	/* reg: CNSTI1 */
/* 30 */	"# reg\n",	/* reg: CNSTI4 */
/* 31 */	"# reg\n",	/* reg: CNSTU1 */
/* 32 */	"# reg\n",	/* reg: CNSTU4 */
/* 33 */	"# reg\n",	/* reg: CNSTP4 */
/* 34 */	"# reg\n",	/* reg: CNSTF4 */
/* 35 */	"\tsb $%1,%0\n",	/* stmt: ASGNI1(addr,reg) */
/* 36 */	"\tsb $%1,%0\n",	/* stmt: ASGNU1(addr,reg) */
/* 37 */	"\tsw $%1,%0\n",	/* stmt: ASGNI4(addr,reg) */
/* 38 */	"\tsw $%1,%0\n",	/* stmt: ASGNU4(addr,reg) */
/* 39 */	"\tsw $%1,%0\n",	/* stmt: ASGNP4(addr,reg) */
/* 40 */	"\tlb $%c,%0\n",	/* reg: INDIRI1(addr) */
/* 41 */	"\tlb $%c,%0; and $%c,$%c,255\n",	/* reg: INDIRU1(addr) */
/* 42 */	"\tlw $%c,%0\n",	/* reg: INDIRI4(addr) */
/* 43 */	"\tlw $%c,%0\n",	/* reg: INDIRU4(addr) */
/* 44 */	"\tlw $%c,%0\n",	/* reg: INDIRP4(addr) */
/* 45 */	"\tlb $%c,%0\n",	/* reg: CVII4(INDIRI1(addr)) */
/* 46 */	"\tlb $%c,%0; and $%c,$%c,255\n",	/* reg: CVUU4(INDIRU1(addr)) */
/* 47 */	"\tlb $%c,%0; and $%c,$%c,255\n",	/* reg: CVUI4(INDIRU1(addr)) */
/* 48 */	"\tlw $%c,%0\n",	/* reg: INDIRF4(addr) */
/* 49 */	"\tsw $%1,%0\n",	/* stmt: ASGNF4(addr,reg) */
/* 50 */	"\tjal __div\n",	/* reg: DIVI4(reg,reg) */
/* 51 */	"\tjal __divu\n",	/* reg: DIVU4(reg,reg) */
/* 52 */	"\tjal __mod\n",	/* reg: MODI4(reg,reg) */
/* 53 */	"\tjal __modu\n",	/* reg: MODU4(reg,reg) */
/* 54 */	"\tjal __mul\n",	/* reg: MULI4(reg,reg) */
/* 55 */	"\tjal __mul\n",	/* reg: MULU4(reg,reg) */
/* 56 */	"%0",	/* rc: con */
/* 57 */	"$%0",	/* rc: reg */
/* 58 */	"\taddu $%c,$%0,%1\n",	/* reg: ADDI4(reg,rc) */
/* 59 */	"\taddu $%c,$%0,%1\n",	/* reg: ADDP4(reg,rc) */
/* 60 */	"\taddu $%c,$%0,%1\n",	/* reg: ADDU4(reg,rc) */
/* 61 */	"\tand $%c,$%0,%1\n",	/* reg: BANDI4(reg,rc) */
/* 62 */	"\tor $%c,$%0,%1\n",	/* reg: BORI4(reg,rc) */
/* 63 */	"\txor $%c,$%0,%1\n",	/* reg: BXORI4(reg,rc) */
/* 64 */	"\tand $%c,$%0,%1\n",	/* reg: BANDU4(reg,rc) */
/* 65 */	"\tor $%c,$%0,%1\n",	/* reg: BORU4(reg,rc) */
/* 66 */	"\txor $%c,$%0,%1\n",	/* reg: BXORU4(reg,rc) */
/* 67 */	"\tsubu $%c,$%0,%1\n",	/* reg: SUBI4(reg,rc) */
/* 68 */	"\tsubu $%c,$%0,%1\n",	/* reg: SUBP4(reg,rc) */
/* 69 */	"\tsubu $%c,$%0,%1\n",	/* reg: SUBU4(reg,rc) */
/* 70 */	"# sll\n",	/* reg: LSHI4(reg,CNSTI4) */
/* 71 */	"# sll\n",	/* reg: LSHU4(reg,CNSTI4) */
/* 72 */	"# sra\n",	/* reg: RSHI4(reg,CNSTI4) */
/* 73 */	"# srl\n",	/* reg: RSHU4(reg,CNSTI4) */
/* 74 */	"\tjal __sll\n",	/* reg: LSHI4(reg,reg) */
/* 75 */	"\tjal __sll\n",	/* reg: LSHU4(reg,reg) */
/* 76 */	"\tjal __sra\n",	/* reg: RSHI4(reg,reg) */
/* 77 */	"\tjal __srl\n",	/* reg: RSHU4(reg,reg) */
/* 78 */	"\tli $30, -1; xor $%c,$%0,$30\n",	/* reg: BCOMI4(reg) */
/* 79 */	"\tli $30, -1; xor $%c,$%0,$30\n",	/* reg: BCOMU4(reg) */
/* 80 */	"\tnegu $%c,$%0\n",	/* reg: NEGI4(reg) */
/* 81 */	"\tmove $%c,$%0\n",	/* reg: LOADI1(reg) */
/* 82 */	"\tmove $%c,$%0\n",	/* reg: LOADU1(reg) */
/* 83 */	"\tmove $%c,$%0\n",	/* reg: LOADI4(reg) */
/* 84 */	"\tmove $%c,$%0\n",	/* reg: LOADP4(reg) */
/* 85 */	"\tmove $%c,$%0\n",	/* reg: LOADU4(reg) */
/* 86 */	"\tmove $%c,$%0\n",	/* reg: LOADF4(reg) */
/* 87 */	"\tjal float32_add\n",	/* reg: ADDF4(reg,reg) */
/* 88 */	"\tjal float32_sub\n",	/* reg: SUBF4(reg,reg) */
/* 89 */	"\tjal float32_mul\n",	/* reg: MULF4(reg,reg) */
/* 90 */	"\tjal float32_div\n",	/* reg: DIVF4(reg,reg) */
/* 91 */	"\tjal float32_neg\n",	/* reg: NEGF4(reg) */
/* 92 */	"\tsb $%0,CVII4_int; lb $%c,CVII4_int\n",	/* reg: CVII4(reg) */
/* 93 */	"\tand $%c,$%0,255\n",	/* reg: CVUI4(reg) */
/* 94 */	"\tand $%c,$%0,255\n",	/* reg: CVUU4(reg) */
/* 95 */	"\t???",	/* reg: CVFF4(reg) */
/* 96 */	"\tjal int32_to_float32\n",	/* reg: CVIF4(reg) */
/* 97 */	"\tjal float32_to_int32_round_to_zero\n",	/* reg: CVFI4(reg) */
/* 98 */	"%a:\n",	/* stmt: LABELV */
/* 99 */	"\tb %0\n",	/* stmt: JUMPV(acon) */
/* 100 */	"\tj $%0\n",	/* stmt: JUMPV(reg) */
/* 101 */	"\tbeq $%0,$%1,%a\n",	/* stmt: EQI4(reg,reg) */
/* 102 */	"\tbeq $%0,$%1,%a\n",	/* stmt: EQU4(reg,reg) */
/* 103 */	"\tbne $%0,$%1,%a\n",	/* stmt: NEI4(reg,reg) */
/* 104 */	"\tbne $%0,$%1,%a\n",	/* stmt: NEU4(reg,reg) */
/* 105 */	"\tslt $30,$%0,$%1\n\tbne $30,$0,%a\n",	/* stmt: LTI4(reg,reg) */
/* 106 */	"\tsltu $30,$%0,$%1\n\tbne $30,$0,%a\n",	/* stmt: LTU4(reg,reg) */
/* 107 */	"\tslt $30,$%1,$%0\n\tbne $30,$0,%a\n",	/* stmt: GTI4(reg,reg) */
/* 108 */	"\tsltu $30,$%1,$%0\n\tbne $30,$0,%a\n",	/* stmt: GTU4(reg,reg) */
/* 109 */	"\tslt $30,$%0,$%1\n\tbeq $30,$0,%a\n",	/* stmt: GEI4(reg,reg) */
/* 110 */	"\tsltu $30,$%0,$%1\n\tbeq $30,$0,%a\n",	/* stmt: GEU4(reg,reg) */
/* 111 */	"\tslt $30,$%1,$%0\n\tbeq $30,$0,%a\n",	/* stmt: LEI4(reg,reg) */
/* 112 */	"\tsltu $30,$%1,$%0\n\tbeq $30,$0,%a\n",	/* stmt: LEU4(reg,reg) */
/* 113 */	"\tbeq $%0,$%1,%a\n",	/* stmt: EQF4(reg,reg) */
/* 114 */	"\tbne $%0,$%1,%a\n",	/* stmt: NEF4(reg,reg) */
/* 115 */	"\tslt $30,$%1,$%0\n\tbeq $30,$0,%a\n",	/* stmt: LEF4(reg,reg) */
/* 116 */	"\tslt $30,$%0,$%1\n\tbne $30,$0,%a\n",	/* stmt: LTF4(reg,reg) */
/* 117 */	"\tslt $30,$%0,$%1\n\tbeq $30,$0,%a\n",	/* stmt: GEF4(reg,reg) */
/* 118 */	"\tslt $30,$%1,$%0\n\tbne $30,$0,%a\n",	/* stmt: GTF4(reg,reg) */
/* 119 */	"\tjal %0\n",	/* reg: CALLF4(ar) */
/* 120 */	"\tjal %0\n",	/* reg: CALLI4(ar) */
/* 121 */	"\tjal %0\n",	/* reg: CALLP4(ar) */
/* 122 */	"\tjal %0\n",	/* reg: CALLU4(ar) */
/* 123 */	"\tjal %0\n",	/* stmt: CALLV(ar) */
/* 124 */	"$%0",	/* ar: reg */
/* 125 */	"%a",	/* ar: CNSTP4 */
/* 126 */	"%a",	/* ar: ADDRGP4 */
/* 127 */	"%a",	/* magic_addr: CNSTP4 */
/* 128 */	"\t.word (%c<<11)|(%0<<21)|(%1<<16)|0x30\n",	/* reg: ADDI4(reg,ADDI4(reg,INDIRI4(magic_addr))) */
/* 129 */	"\t.word (%c<<11)|(%0<<21)|(%1<<16)|0x31\n",	/* reg: SUBI4(reg,ADDI4(reg,INDIRI4(magic_addr))) */
/* 130 */	"\t.word (%c<<11)|(%0<<21)|(%1<<16)|0x32\n",	/* reg: ADDI4(reg,SUBI4(reg,INDIRI4(magic_addr))) */
/* 131 */	"\t.word (%c<<11)|(%0<<21)|(%1<<16)|0x33\n",	/* reg: SUBI4(reg,SUBI4(reg,INDIRI4(magic_addr))) */
/* 132 */	"\t.word (%c<<11)|(%2<<21)|(%2<<16)|0x35\n \t.word (%c<<11)|(%0<<21)|(%1<<16)|0x34\n",	/* reg: SUBI4(reg,SUBI4(reg,ADDI4(reg,INDIRI4(magic_addr)))) */
/* 133 */	"# ret\n",	/* stmt: RETF4(reg) */
/* 134 */	"# ret\n",	/* stmt: RETI4(reg) */
/* 135 */	"# ret\n",	/* stmt: RETU4(reg) */
/* 136 */	"# ret\n",	/* stmt: RETP4(reg) */
/* 137 */	"# ret\n",	/* stmt: RETV(reg) */
/* 138 */	"# arg\n",	/* stmt: ARGF4(reg) */
/* 139 */	"# arg\n",	/* stmt: ARGI4(reg) */
/* 140 */	"# arg\n",	/* stmt: ARGP4(reg) */
/* 141 */	"# arg\n",	/* stmt: ARGU4(reg) */
/* 142 */	"# argb %0\n",	/* stmt: ARGB(INDIRB(reg)) */
/* 143 */	"# asgnb %0 %1\n",	/* stmt: ASGNB(reg,INDIRB(reg)) */
};

static char _isinstruction[] = {
/* 0 */	0,
/* 1 */	1,	/* # read register\n */
/* 2 */	1,	/* # read register\n */
/* 3 */	1,	/* # read register\n */
/* 4 */	1,	/* # read register\n */
/* 5 */	1,	/* # read register\n */
/* 6 */	1,	/* # read register\n */
/* 7 */	1,	/* # write register\n */
/* 8 */	1,	/* # write register\n */
/* 9 */	1,	/* # write register\n */
/* 10 */	1,	/* # write register\n */
/* 11 */	1,	/* # write register\n */
/* 12 */	1,	/* # write register\n */
/* 13 */	0,	/* %a */
/* 14 */	0,	/* %a */
/* 15 */	0,	/* %a */
/* 16 */	0,	/* %a */
/* 17 */	0,	/* %a */
/* 18 */	0,	/*  */
/* 19 */	0,	/* %0 */
/* 20 */	0,	/* %a */
/* 21 */	0,	/* %1($%0) */
/* 22 */	0,	/* %1($%0) */
/* 23 */	0,	/* %1($%0) */
/* 24 */	0,	/* %0 */
/* 25 */	0,	/* ($%0) */
/* 26 */	0,	/* %a+%F($sp) */
/* 27 */	0,	/* %a+%F($sp) */
/* 28 */	1,	/* \tla $%c,%0\n */
/* 29 */	1,	/* # reg\n */
/* 30 */	1,	/* # reg\n */
/* 31 */	1,	/* # reg\n */
/* 32 */	1,	/* # reg\n */
/* 33 */	1,	/* # reg\n */
/* 34 */	1,	/* # reg\n */
/* 35 */	1,	/* \tsb $%1,%0\n */
/* 36 */	1,	/* \tsb $%1,%0\n */
/* 37 */	1,	/* \tsw $%1,%0\n */
/* 38 */	1,	/* \tsw $%1,%0\n */
/* 39 */	1,	/* \tsw $%1,%0\n */
/* 40 */	1,	/* \tlb $%c,%0\n */
/* 41 */	1,	/* \tlb $%c,%0; and $%c,$%c,255\n */
/* 42 */	1,	/* \tlw $%c,%0\n */
/* 43 */	1,	/* \tlw $%c,%0\n */
/* 44 */	1,	/* \tlw $%c,%0\n */
/* 45 */	1,	/* \tlb $%c,%0\n */
/* 46 */	1,	/* \tlb $%c,%0; and $%c,$%c,255\n */
/* 47 */	1,	/* \tlb $%c,%0; and $%c,$%c,255\n */
/* 48 */	1,	/* \tlw $%c,%0\n */
/* 49 */	1,	/* \tsw $%1,%0\n */
/* 50 */	1,	/* \tjal __div\n */
/* 51 */	1,	/* \tjal __divu\n */
/* 52 */	1,	/* \tjal __mod\n */
/* 53 */	1,	/* \tjal __modu\n */
/* 54 */	1,	/* \tjal __mul\n */
/* 55 */	1,	/* \tjal __mul\n */
/* 56 */	0,	/* %0 */
/* 57 */	0,	/* $%0 */
/* 58 */	1,	/* \taddu $%c,$%0,%1\n */
/* 59 */	1,	/* \taddu $%c,$%0,%1\n */
/* 60 */	1,	/* \taddu $%c,$%0,%1\n */
/* 61 */	1,	/* \tand $%c,$%0,%1\n */