x86linux.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 2,383 行 · 第 1/5 页

/* 152 */	1,	/* mull %1\n */
/* 153 */	1,	/* xorl %%edx,%%edx\ndivl %1\n */
/* 154 */	1,	/* xorl %%edx,%%edx\ndivl %1\n */
/* 155 */	1,	/* cdq\nidivl %1\n */
/* 156 */	1,	/* cdq\nidivl %1\n */
/* 157 */	1,	/* movl %0,%c\n */
/* 158 */	1,	/* movl %0,%c\n */
/* 159 */	1,	/* movsbl %0,%c\n */
/* 160 */	1,	/* movswl %0,%c\n */
/* 161 */	1,	/* movzbl %0,%c\n */
/* 162 */	1,	/* movzwl %0,%c\n */
/* 163 */	1,	/* # extend\n */
/* 164 */	1,	/* # extend\n */
/* 165 */	1,	/* # extend\n */
/* 166 */	1,	/* # extend\n */
/* 167 */	1,	/* # truncate\n */
/* 168 */	1,	/* # truncate\n */
/* 169 */	1,	/* # truncate\n */
/* 170 */	1,	/* # truncate\n */
/* 171 */	0,	/* %0 */
/* 172 */	0,	/* %0 */
/* 173 */	0,	/* $%a */
/* 174 */	0,	/* $%a */
/* 175 */	1,	/* movb %1,%0\n */
/* 176 */	1,	/* movw %1,%0\n */
/* 177 */	1,	/* movl %1,%0\n */
/* 178 */	1,	/* movb %1,%0\n */
/* 179 */	1,	/* movw %1,%0\n */
/* 180 */	1,	/* movl %1,%0\n */
/* 181 */	1,	/* movl %1,%0\n */
/* 182 */	1,	/* pushl %0\n */
/* 183 */	1,	/* pushl %0\n */
/* 184 */	1,	/* pushl %0\n */
/* 185 */	1,	/* movl $%a,%%ecx\nrep\nmovsb\n */
/* 186 */	1,	/* subl $%a,%%esp\nmovl %%esp,%%edi\nmovl $%a,%%ecx\nrep\nmovsb\n */
/* 187 */	0,	/* l %0 */
/* 188 */	0,	/* s %0 */
/* 189 */	0,	/* s %0 */
/* 190 */	0,	/* l %0 */
/* 191 */	1,	/* fld%0\n */
/* 192 */	1,	/* fstpl %0\n */
/* 193 */	1,	/* fstps %0\n */
/* 194 */	1,	/* fstps %0\n */
/* 195 */	1,	/* subl $8,%%esp\nfstpl (%%esp)\n */
/* 196 */	1,	/* subl $4,%%esp\nfstps (%%esp)\n */
/* 197 */	1,	/* fchs\n */
/* 198 */	1,	/* fchs\n */
/* 199 */	0,	/* %0 */
/* 200 */	0,	/* p %%st(1),%%st */
/* 201 */	1,	/* fadd%1\n */
/* 202 */	1,	/* fadd%1\n */
/* 203 */	1,	/* fdiv%1\n */
/* 204 */	1,	/* fdiv%1\n */
/* 205 */	1,	/* fmul%1\n */
/* 206 */	1,	/* fmul%1\n */
/* 207 */	1,	/* fsub%1\n */
/* 208 */	1,	/* fsub%1\n */
/* 209 */	1,	/* # CVFF8\n */
/* 210 */	1,	/* sub $4,%%esp\nfstps (%%esp)\nflds (%%esp)\naddl $4,%%esp\n */
/* 211 */	1,	/* fistpl %0\n */
/* 212 */	1,	/* subl $4,%%esp\nfistpl 0(%%esp)\npopl %c\n */
/* 213 */	1,	/* fildl %0\n */
/* 214 */	1,	/* pushl %0\nfildl (%%esp)\naddl $4,%%esp\n */
/* 215 */	1,	/* fildl %0\n */
/* 216 */	1,	/* pushl %0\nfildl (%%esp)\naddl $4,%%esp\n */
/* 217 */	0,	/* %a */
/* 218 */	0,	/* *%0 */
/* 219 */	0,	/* *%0 */
/* 220 */	1,	/* %a:\n */
/* 221 */	1,	/* jmp %0\n */
/* 222 */	1,	/* cmpl %1,%0\nje %a\n */
/* 223 */	1,	/* cmpl %1,%0\njge %a\n */
/* 224 */	1,	/* cmpl %1,%0\njg %a\n */
/* 225 */	1,	/* cmpl %1,%0\njle %a\n */
/* 226 */	1,	/* cmpl %1,%0\njl %a\n */
/* 227 */	1,	/* cmpl %1,%0\njne %a\n */
/* 228 */	1,	/* cmpl %1,%0\njae %a\n */
/* 229 */	1,	/* cmpl %1,%0\nja  %a\n */
/* 230 */	1,	/* cmpl %1,%0\njbe %a\n */
/* 231 */	1,	/* cmpl %1,%0\njb  %a\n */
/* 232 */	1,	/* cmpl %1,%0\nje %a\n */
/* 233 */	1,	/* cmpl %1,%0\njge %a\n */
/* 234 */	1,	/* cmpl %1,%0\njg %a\n */
/* 235 */	1,	/* cmpl %1,%0\njle %a\n */
/* 236 */	1,	/* cmpl %1,%0\njl %a\n */
/* 237 */	1,	/* cmpl %1,%0\njne %a\n */
/* 238 */	1,	/* cmpl %1,%0\nje %a\n */
/* 239 */	1,	/* cmpl %1,%0\njae %a\n */
/* 240 */	1,	/* cmpl %1,%0\nja %a\n */
/* 241 */	1,	/* cmpl %1,%0\njbe %a\n */
/* 242 */	1,	/* cmpl %1,%0\njb %a\n */
/* 243 */	1,	/* cmpl %1,%0\njne %a\n */
/* 244 */	1,	/* testl %1,%0\nje %a\n */
/* 245 */	1,	/* testl %1,%0\njne %a\n */
/* 246 */	1,	/* testw %1,%0\nje %a\n */
/* 247 */	1,	/* testw %1,%0\njne %a\n */
/* 248 */	1,	/* testw %1,%0\nje %a\n */
/* 249 */	1,	/* testw %1,%0\njne %a\n */
/* 250 */	1,	/* testb %1,%0\nje %a\n */
/* 251 */	0,	/* l %0 */
/* 252 */	0,	/* s %0 */
/* 253 */	0,	/* s %0 */
/* 254 */	0,	/* p */
/* 255 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\nje %a\n */
/* 256 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njbe %a\n */
/* 257 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njb %a\n */
/* 258 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njae %a\n */
/* 259 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\nja %a\n */
/* 260 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njne %a\n */
/* 261 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\nje %a\n */
/* 262 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njbe %a\n */
/* 263 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njb %a\n */
/* 264 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njae %a\n */
/* 265 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\nja %a\n */
/* 266 */	1,	/* fcomp%0\nfstsw %%ax\nsahf\njne %a\n */
/* 267 */	1,	/* fidivl %1\n */
/* 268 */	1,	/* fidivrl %0\n */
/* 269 */	1,	/* fidivs %1\n */
/* 270 */	1,	/* fidivrs %0\n */
/* 271 */	1,	/* fimull %1\n */
/* 272 */	1,	/* fimuls %1\n */
/* 273 */	1,	/* fisubl %1\n */
/* 274 */	1,	/* fisubrl %0\n */
/* 275 */	1,	/* fisubs %1\n */
/* 276 */	1,	/* fisubrs %0\n */
/* 277 */	1,	/* fiaddl %1\n */
/* 278 */	1,	/* fiadds %1\n */
/* 279 */	1,	/* fdivs %1\n */
/* 280 */	1,	/* fsubs %1\n */
/* 281 */	1,	/* fmuls %1\n */
/* 282 */	1,	/* fdivs %1\n */
/* 283 */	1,	/* fld%0\n */
/* 284 */	1,	/* call %0\naddl $%a,%%esp\n */
/* 285 */	1,	/* call %0\naddl $%a,%%esp\n */
/* 286 */	1,	/* call %0\naddl $%a,%%esp\n */
/* 287 */	1,	/* call %0\n */
/* 288 */	1,	/* call %0\n */
/* 289 */	1,	/* call %0\n */
/* 290 */	1,	/* call %0\naddl $%a,%%esp\n */
/* 291 */	1,	/* call %0\n */
/* 292 */	1,	/* call %0\naddl $%a,%%esp\n */
/* 293 */	1,	/* call %0\n */
/* 294 */	1,	/* call %0\naddl $%a,%%esp\nfstp %%st(0)\n */
/* 295 */	1,	/* call %0\nfstp %%st(0)\n */
/* 296 */	1,	/* call %0\naddl $%a,%%esp\n */
/* 297 */	1,	/* call %0\n */
/* 298 */	1,	/* call %0\naddl $%a,%%esp\nfstp %%st(0)\n */
/* 299 */	1,	/* call %0\nfstp %%st(0)\n */
/* 300 */	1,	/* # ret\n */
/* 301 */	1,	/* # ret\n */
/* 302 */	1,	/* # ret\n */
/* 303 */	1,	/* # ret\n */
/* 304 */	1,	/* # ret\n */
};

static char *_string[] = {
/* 0 */	0,
/* 1 */	"reg: INDIRI1(VREGP)",
/* 2 */	"reg: INDIRU1(VREGP)",
/* 3 */	"reg: INDIRI2(VREGP)",
/* 4 */	"reg: INDIRU2(VREGP)",
/* 5 */	"reg: INDIRI4(VREGP)",
/* 6 */	"reg: INDIRP4(VREGP)",
/* 7 */	"reg: INDIRU4(VREGP)",
/* 8 */	"reg: INDIRI8(VREGP)",
/* 9 */	"reg: INDIRP8(VREGP)",
/* 10 */	"reg: INDIRU8(VREGP)",
/* 11 */	"freg: INDIRF4(VREGP)",
/* 12 */	"freg: INDIRF8(VREGP)",
/* 13 */	"stmt: ASGNI1(VREGP,reg)",
/* 14 */	"stmt: ASGNU1(VREGP,reg)",
/* 15 */	"stmt: ASGNI2(VREGP,reg)",
/* 16 */	"stmt: ASGNU2(VREGP,reg)",
/* 17 */	"stmt: ASGNF4(VREGP,reg)",
/* 18 */	"stmt: ASGNI4(VREGP,reg)",
/* 19 */	"stmt: ASGNP4(VREGP,reg)",
/* 20 */	"stmt: ASGNU4(VREGP,reg)",
/* 21 */	"stmt: ASGNF8(VREGP,reg)",
/* 22 */	"stmt: ASGNI8(VREGP,reg)",
/* 23 */	"stmt: ASGNP8(VREGP,reg)",
/* 24 */	"stmt: ASGNU8(VREGP,reg)",
/* 25 */	"cnst: CNSTI1",
/* 26 */	"cnst: CNSTU1",
/* 27 */	"cnst: CNSTI2",
/* 28 */	"cnst: CNSTU2",
/* 29 */	"cnst: CNSTI4",
/* 30 */	"cnst: CNSTU4",
/* 31 */	"cnst: CNSTP4",
/* 32 */	"cnst: CNSTI8",
/* 33 */	"cnst: CNSTU8",
/* 34 */	"cnst: CNSTP8",
/* 35 */	"con: cnst",
/* 36 */	"stmt: reg",
/* 37 */	"stmt: freg",
/* 38 */	"acon: ADDRGP4",
/* 39 */	"acon: ADDRGP8",
/* 40 */	"acon: cnst",
/* 41 */	"baseaddr: ADDRGP4",
/* 42 */	"base: reg",
/* 43 */	"base: ADDI4(reg,acon)",
/* 44 */	"base: ADDP4(reg,acon)",
/* 45 */	"base: ADDU4(reg,acon)",
/* 46 */	"base: ADDRFP4",
/* 47 */	"base: ADDRLP4",
/* 48 */	"index: reg",
/* 49 */	"index: LSHI4(reg,con1)",
/* 50 */	"index: LSHI4(reg,con2)",
/* 51 */	"index: LSHI4(reg,con3)",
/* 52 */	"index: LSHU4(reg,con1)",
/* 53 */	"index: LSHU4(reg,con2)",
/* 54 */	"index: LSHU4(reg,con3)",
/* 55 */	"con0: CNSTI4",
/* 56 */	"con0: CNSTU4",
/* 57 */	"con1: CNSTI4",
/* 58 */	"con1: CNSTU4",
/* 59 */	"con2: CNSTI4",
/* 60 */	"con2: CNSTU4",
/* 61 */	"con3: CNSTI4",
/* 62 */	"con3: CNSTU4",
/* 63 */	"addr: base",
/* 64 */	"addr: baseaddr",
/* 65 */	"addr: ADDI4(index,baseaddr)",
/* 66 */	"addr: ADDP4(index,baseaddr)",
/* 67 */	"addr: ADDU4(index,baseaddr)",
/* 68 */	"addr: ADDI4(reg,baseaddr)",
/* 69 */	"addr: ADDP4(reg,baseaddr)",
/* 70 */	"addr: ADDU4(reg,baseaddr)",
/* 71 */	"addr: ADDI4(index,reg)",
/* 72 */	"addr: ADDP4(index,reg)",
/* 73 */	"addr: ADDU4(index,reg)",
/* 74 */	"addr: index",
/* 75 */	"mem1: INDIRI1(addr)",
/* 76 */	"mem1: INDIRU1(addr)",
/* 77 */	"mem2: INDIRI2(addr)",
/* 78 */	"mem2: INDIRU2(addr)",
/* 79 */	"mem4: INDIRI4(addr)",
/* 80 */	"mem4: INDIRU4(addr)",
/* 81 */	"mem4: INDIRP4(addr)",
/* 82 */	"rc: reg",
/* 83 */	"rc: con",
/* 84 */	"mr: reg",
/* 85 */	"mr: mem4",
/* 86 */	"mr1: reg",
/* 87 */	"mr1: mem1",
/* 88 */	"mr2: reg",
/* 89 */	"mr2: mem2",
/* 90 */	"mrc: mem4",
/* 91 */	"mrc: mem1",
/* 92 */	"mrc: mem2",
/* 93 */	"mrc: rc",
/* 94 */	"reg: addr",
/* 95 */	"reg: mr",
/* 96 */	"reg: mr1",
/* 97 */	"reg: mr2",
/* 98 */	"reg: con",
/* 99 */	"reg: LOADI1(reg)",
/* 100 */	"reg: LOADI2(reg)",
/* 101 */	"reg: LOADI4(reg)",
/* 102 */	"reg: LOADU1(reg)",
/* 103 */	"reg: LOADU2(reg)",
/* 104 */	"reg: LOADU4(reg)",
/* 105 */	"reg: LOADP4(reg)",
/* 106 */	"reg: ADDI4(reg,mrc)",
/* 107 */	"reg: ADDP4(reg,mrc)",
/* 108 */	"reg: ADDU4(reg,mrc)",
/* 109 */	"reg: SUBI4(reg,mrc)",
/* 110 */	"reg: SUBP4(reg,mrc)",
/* 111 */	"reg: SUBU4(reg,mrc)",
/* 112 */	"reg: BANDI4(reg,mrc)",
/* 113 */	"reg: BORI4(reg,mrc)",
/* 114 */	"reg: BXORI4(reg,mrc)",
/* 115 */	"reg: BANDU4(reg,mrc)",
/* 116 */	"reg: BORU4(reg,mrc)",
/* 117 */	"reg: BXORU4(reg,mrc)",
/* 118 */	"stmt: ASGNI4(addr,ADDI4(mem4,con1))",
/* 119 */	"stmt: ASGNI4(addr,ADDU4(mem4,con1))",
/* 120 */	"stmt: ASGNP4(addr,ADDP4(mem4,con1))",
/* 121 */	"stmt: ASGNI4(addr,SUBI4(mem4,con1))",
/* 122 */	"stmt: ASGNI4(addr,SUBU4(mem4,con1))",
/* 123 */	"stmt: ASGNP4(addr,SUBP4(mem4,con1))",
/* 124 */	"stmt: ASGNI4(addr,ADDI4(mem4,rc))",
/* 125 */	"stmt: ASGNI4(addr,SUBI4(mem4,rc))",
/* 126 */	"stmt: ASGNU4(addr,ADDU4(mem4,rc))",
/* 127 */	"stmt: ASGNU4(addr,SUBU4(mem4,rc))",
/* 128 */	"stmt: ASGNI4(addr,BANDI4(mem4,rc))",
/* 129 */	"stmt: ASGNI4(addr,BORI4(mem4,rc))",
/* 130 */	"stmt: ASGNI4(addr,BXORI4(mem4,rc))",
/* 131 */	"stmt: ASGNU4(addr,BANDU4(mem4,rc))",
/* 132 */	"stmt: ASGNU4(addr,BORU4(mem4,rc))",
/* 133 */	"stmt: ASGNU4(addr,BXORU4(mem4,rc))",
/* 134 */	"reg: BCOMI4(reg)",
/* 135 */	"reg: BCOMU4(reg)",
/* 136 */	"reg: NEGI4(reg)",
/* 137 */	"stmt: ASGNI4(addr,BCOMI4(mem4))",
/* 138 */	"stmt: ASGNU4(addr,BCOMU4(mem4))",
/* 139 */	"stmt: ASGNI4(addr,NEGI4(mem4))",
/* 140 */	"reg: LSHI4(reg,rc5)",
/* 141 */	"reg: LSHU4(reg,rc5)",
/* 142 */	"reg: RSHI4(reg,rc5)",
/* 143 */	"reg: RSHU4(reg,rc5)",
/* 144 */	"stmt: ASGNI4(addr,LSHI4(mem4,rc5))",
/* 145 */	"stmt: ASGNI4(addr,LSHU4(mem4,rc5))",
/* 146 */	"stmt: ASGNI4(addr,RSHI4(mem4,rc5))",
/* 147 */	"stmt: ASGNI4(addr,RSHU4(mem4,rc5))",
/* 148 */	"rc5: CNSTI4",
/* 149 */	"rc5: reg",
/* 150 */	"reg: MULI4(reg,mrc)",
/* 151 */	"reg: MULI4(con,mr)",
/* 152 */	"reg: MULU4(reg,mr)",
/* 153 */	"reg: DIVU4(reg,reg)",
/* 154 */	"reg: MODU4(reg,reg)",
/* 155 */	"reg: DIVI4(reg,reg)",
/* 156 */	"reg: MODI4(reg,reg)",
/* 157 */	"reg: CVPU4(reg)",
/* 158 */	"reg: CVUP4(reg)",
/* 159 */	"reg: CVII4(INDIRI1(addr))",
/* 160 */	"reg: CVII4(INDIRI2(addr))",
/* 161 */	"reg: CVUU4(INDIRU1(addr))",
/* 162 */	"reg: CVUU4(INDIRU2(addr))",
/* 163 */	"reg: CVII4(reg)",
/* 164 */	"reg: CVIU4(reg)",
/* 165 */	"reg: CVUI4(reg)",
/* 166 */	"reg: CVUU4(reg)",
/* 167 */	"reg: CVII1(reg)",
/* 168 */	"reg: CVII2(reg)",
/* 169 */	"reg: CVUU1(reg)",
/* 170 */	"reg: CVUU2(reg)",
/* 171 */	"mrca: mem4",
/* 172 */	"mrca: rc",
/* 173 */	"mrca: ADDRGP4",
/* 174 */	"mrca: ADDRGP8",
/* 175 */	"stmt: ASGNI1(addr,rc)",
/* 176 */	"stmt: ASGNI2(addr,rc)",
/* 177 */	"stmt: ASGNI4(addr,rc)",
/* 178 */	"stmt: ASGNU1(addr,rc)",
/* 179 */	"stmt: ASGNU2(addr,rc)",
/* 180 */	"stmt: ASGNU4(addr,rc)",
/* 181 */	"stmt: ASGNP4(addr,rc)",
/* 182 */	"stmt: ARGI4(mrca)",
/* 183 */	"stmt: ARGU4(mrca)",
/* 184 */	"stmt: ARGP4(mrca)",
/* 185 */	"stmt: ASGNB(reg,INDIRB(reg))",
/* 186 */	"stmt: ARGB(INDIRB(reg))",
/* 187 */	"memf: INDIRF8(addr)",
/* 188 */	"memf: INDIRF4(addr)",
/* 189 */	"memf: CVFF8(INDIRF4(addr))",
/* 190 */	"memf: CVFF4(INDIRF8(addr))",
/* 191 */	"freg: memf",
/* 192 */	"stmt: ASGNF8(addr,freg)",
/* 193 */	"stmt: ASGNF4(addr,freg)",
/* 194 */	"stmt: ASGNF4(addr,CVFF4(freg))",
/* 195 */	"stmt: ARGF8(freg)",
/* 196 */	"stmt: ARGF4(freg)",
/* 197 */	"freg: NEGF8(freg)",
/* 198 */	"freg: NEGF4(freg)",
/* 199 */	"flt: memf",
/* 200 */	"flt: freg",
/* 201 */	"freg: ADDF4(freg,flt)",
/* 202 */	"freg: ADDF8(freg,flt)",
/* 203 */	"freg: DIVF4(freg,flt)",
/* 204 */	"freg: DIVF8(freg,flt)",
/* 205 */	"freg: MULF4(freg,flt)",
/* 206 */	"freg: MULF8(freg,flt)",
/* 207 */	"freg: SUBF4(freg,flt)",
/* 208 */	"freg: SUBF8(freg,flt)",
/* 209 */	"freg: CVFF8(freg)",
/* 210 */	"freg: CVFF4(freg)",
/* 211 */	"stmt: ASGNI4(addr,CVFI4(freg))",
/* 212 */	"reg: CVFI4(freg)",
/* 213 */	"freg: CVIF8(INDIRI4(addr))",
/* 214 */	"freg: CVIF8(reg)",
/* 215 */	"freg: CVIF4(INDIRI4(addr))",
/* 216 */	"freg: CVIF4(reg)",
/* 217 */	"addrj: ADDRGP4",
/* 218 */	"addrj: reg",
/* 219 */	"addrj: mem4",
/* 220 */	"stmt: LABELV",
/* 221 */	"stmt: JUMPV(addrj)",
/* 222 */	"stmt: EQI4(mem4,rc)",
/* 223 */	"stmt: GEI4(mem4,rc)",
/* 224 */	"stmt: GTI4(mem4,rc)",
/* 225 */	"stmt: LEI4(mem4,rc)",
/* 226 */	"stmt: LTI4(mem4,rc)",
/* 227 */	"stmt: NEI4(mem4,rc)",
/* 228 */	"stmt: GEU4(mem4,rc)",
/* 229 */	"stmt: GTU4(mem4,rc)",
/* 230 */	"stmt: LEU4(mem4,rc)",
/* 231 */	"stmt: LTU4(mem4,rc)",
/* 232 */	"stmt: EQI4(reg,mrc)",
/* 233 */	"stmt: GEI4(reg,mrc)",
/* 234 */	"stmt: GTI4(reg,mrc)",
/* 235 */	"stmt: LEI4(reg,mrc)",
/* 236 */	"stmt: LTI4(reg,mrc)",
/* 237 */	"stmt: NEI4(reg,mrc)",
/* 238 */	"stmt: EQU4(reg,mrc)",
/* 239 */	"stmt: GEU4(reg,mrc)",
/* 240 */	"stmt: GTU4(reg,mrc)",
/* 241 */	"stmt: LEU4(reg,mrc)",
/* 242 */	"stmt: LTU4(reg,mrc)",
/* 243 */	"stmt: NEU4(reg,mrc)",
/* 244 */	"stmt: EQI4(BANDU4(mr,con),con0)",
/* 245 */	"stmt: NEI4(BANDU4(mr,con),con0)",
/* 246 */	"stmt: EQI4(BANDU4(CVII2(INDIRI2(addr)),con),con0)",
/* 247 */	"stmt: NEI4(BANDU4(CVII2(INDIRI2(addr)),con),con0)",
/* 248 */	"stmt: EQI4(BANDU4(CVIU2(INDIRI2(addr)),con),con0)",
/* 249 */	"stmt: NEI4(BANDU4(CVIU2(INDIRI2(addr)),con),con0)",
/* 250 */	"stmt: EQI4(BANDU4(CVII1(INDIRI1(addr)),con),con0)",
/* 251 */	"cmpf: INDIRF8(addr)",
/* 252 */	"cmpf: INDIRF4(addr)",
/* 253 */	"cmpf: CVFF8(INDIRF4(addr))",
/* 254 */	"cmpf: freg",
/* 255 */	"stmt: EQF8(cmpf,freg)",
/* 256 */	"stmt: GEF8(cmpf,freg)",
/* 257 */	"stmt: GTF8(cmpf,freg)",
/* 258 */	"stmt: LEF8(cmpf,freg)",
/* 259 */	"stmt: LTF8(cmpf,freg)",
/* 260 */	"stmt: NEF8(cmpf,freg)",
/* 261 */	"stmt: EQF4(cmpf,freg)",
/* 262 */	"stmt: GEF4(cmpf,freg)",
/* 263 */	"stmt: GTF4(cmpf,freg)",
/* 264 */	"stmt: LEF4(cmpf,freg)",
/* 265 */	"stmt: LTF4(cmpf,freg)",
/* 266 */	"stmt: NEF4(cmpf,freg)",
/* 267 */	"freg: DIVF8(freg,CVIF8(INDIRI4(addr)))",
/* 268 */	"freg: DIVF8(CVIF8(INDIRI4(addr)),freg)",
/* 269 */	"freg: DIVF8(freg,CVIF8(CVII2(INDIRI2(addr))))",
/* 270 */	"freg: DIVF8(CVIF8(CVII2(INDIRI2(addr))),freg)",
/* 271 */	"freg: MULF8(freg,CVIF8(INDIRI4(addr)))",
/* 272 */	"freg: MULF8(freg,CVIF8(CVII2(INDIRI2(addr))))",
/* 273 */	"freg: SUBF8(freg,CVIF8(INDIRI4(addr)))",
/* 274 */	"freg: SUBF8(CVIF8(INDIRI4(addr)),freg)",
/* 275 */	"freg: SUBF8(freg,CVIF8(CVII2(INDIRI2(addr))))",
/* 276 */	"freg: SUBF8(CVIF8(CVII2(INDIRI2(addr))),freg)",
/* 277 */	"freg: ADDF8(freg,CVIF8(INDIRI4(addr)))",
/* 278 */	"freg: ADDF8(freg,CVIF8(CVII2(INDIRI2(addr))))",
/* 279 */	"freg: ADDF8(freg,CVFF8(INDIRF4(addr)))",
/* 280 */	"freg: SUBF8(freg,CVFF8(INDIRF4(addr)))",
/* 281 */	"freg: MULF8(freg,CVFF8(INDIRF4(addr)))",
/* 282 */	"freg: DIVF8(freg,CVFF8(INDIRF4(addr)))",
/* 283 */	"freg: LOADF8(memf)",
/* 284 */	"reg: CALLI4(addrj)",
/* 285 */	"reg: CALLU4(addrj)",
/* 286 */	"reg: CALLP4(addrj)",
/* 287 */	"reg: CALLI4(addrj)",
/* 288 */	"reg: CALLU4(addrj)",
/* 289 */	"reg: CALLP4(addrj)",
/* 290 */	"stmt: CALLV(addrj)",
/* 291 */	"stmt: CALLV(addrj)",
/* 292 */	"freg: CALLF4(addrj)",
/* 293 */	"freg: CALLF4(addrj)",
/* 294 */	"stmt: CALLF4(addrj)",
/* 295 */	"stmt: CALLF4(addrj)",
/* 296 */	"freg: CALLF8(addrj)",
/* 297 */	"freg: CALLF8(addrj)",
/* 298 */	"stmt: CALLF8(addrj)",
/* 299 */	"stmt: CALLF8(addrj)",
/* 300 */	"stmt: RETI4(reg)",
/* 301 */	"stmt: RETU4(reg)",
/* 302 */	"stmt: RETP4(reg)",
/* 303 */	"stmt: RETF4(freg)",
/* 304 */	"stmt: RETF8(freg)",
};

static short _decode_stmt[] = {
	0,
	13,
	14,
	15,
	16,
	17,
	18,
	19,
	20,
	21,
	22,
	23,
	24,