x86linux.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 2,383 行 · 第 1/5 页

	_nts_37,	/* 291 */
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	_nts_1,	/* 300 */
	_nts_1,	/* 301 */
	_nts_1,	/* 302 */
	_nts_3,	/* 303 */
	_nts_3,	/* 304 */
};

static char *_templates[] = {
/* 0 */	0,
/* 1 */	"# read register\n",	/* reg: INDIRI1(VREGP) */
/* 2 */	"# read register\n",	/* reg: INDIRU1(VREGP) */
/* 3 */	"# read register\n",	/* reg: INDIRI2(VREGP) */
/* 4 */	"# read register\n",	/* reg: INDIRU2(VREGP) */
/* 5 */	"# read register\n",	/* reg: INDIRI4(VREGP) */
/* 6 */	"# read register\n",	/* reg: INDIRP4(VREGP) */
/* 7 */	"# read register\n",	/* reg: INDIRU4(VREGP) */
/* 8 */	"# read register\n",	/* reg: INDIRI8(VREGP) */
/* 9 */	"# read register\n",	/* reg: INDIRP8(VREGP) */
/* 10 */	"# read register\n",	/* reg: INDIRU8(VREGP) */
/* 11 */	"# read register\n",	/* freg: INDIRF4(VREGP) */
/* 12 */	"# read register\n",	/* freg: INDIRF8(VREGP) */
/* 13 */	"# write register\n",	/* stmt: ASGNI1(VREGP,reg) */
/* 14 */	"# write register\n",	/* stmt: ASGNU1(VREGP,reg) */
/* 15 */	"# write register\n",	/* stmt: ASGNI2(VREGP,reg) */
/* 16 */	"# write register\n",	/* stmt: ASGNU2(VREGP,reg) */
/* 17 */	"# write register\n",	/* stmt: ASGNF4(VREGP,reg) */
/* 18 */	"# write register\n",	/* stmt: ASGNI4(VREGP,reg) */
/* 19 */	"# write register\n",	/* stmt: ASGNP4(VREGP,reg) */
/* 20 */	"# write register\n",	/* stmt: ASGNU4(VREGP,reg) */
/* 21 */	"# write register\n",	/* stmt: ASGNF8(VREGP,reg) */
/* 22 */	"# write register\n",	/* stmt: ASGNI8(VREGP,reg) */
/* 23 */	"# write register\n",	/* stmt: ASGNP8(VREGP,reg) */
/* 24 */	"# write register\n",	/* stmt: ASGNU8(VREGP,reg) */
/* 25 */	"%a",	/* cnst: CNSTI1 */
/* 26 */	"%a",	/* cnst: CNSTU1 */
/* 27 */	"%a",	/* cnst: CNSTI2 */
/* 28 */	"%a",	/* cnst: CNSTU2 */
/* 29 */	"%a",	/* cnst: CNSTI4 */
/* 30 */	"%a",	/* cnst: CNSTU4 */
/* 31 */	"%a",	/* cnst: CNSTP4 */
/* 32 */	"%a",	/* cnst: CNSTI8 */
/* 33 */	"%a",	/* cnst: CNSTU8 */
/* 34 */	"%a",	/* cnst: CNSTP8 */
/* 35 */	"$%0",	/* con: cnst */
/* 36 */	"",	/* stmt: reg */
/* 37 */	"",	/* stmt: freg */
/* 38 */	"%a",	/* acon: ADDRGP4 */
/* 39 */	"%a",	/* acon: ADDRGP8 */
/* 40 */	"%0",	/* acon: cnst */
/* 41 */	"%a",	/* baseaddr: ADDRGP4 */
/* 42 */	"(%0)",	/* base: reg */
/* 43 */	"%1(%0)",	/* base: ADDI4(reg,acon) */
/* 44 */	"%1(%0)",	/* base: ADDP4(reg,acon) */
/* 45 */	"%1(%0)",	/* base: ADDU4(reg,acon) */
/* 46 */	"%a(%%ebp)",	/* base: ADDRFP4 */
/* 47 */	"%a(%%ebp)",	/* base: ADDRLP4 */
/* 48 */	"%0",	/* index: reg */
/* 49 */	"%0,2",	/* index: LSHI4(reg,con1) */
/* 50 */	"%0,4",	/* index: LSHI4(reg,con2) */
/* 51 */	"%0,8",	/* index: LSHI4(reg,con3) */
/* 52 */	"%0,2",	/* index: LSHU4(reg,con1) */
/* 53 */	"%0,4",	/* index: LSHU4(reg,con2) */
/* 54 */	"%0,8",	/* index: LSHU4(reg,con3) */
/* 55 */	"1",	/* con0: CNSTI4 */
/* 56 */	"1",	/* con0: CNSTU4 */
/* 57 */	"1",	/* con1: CNSTI4 */
/* 58 */	"1",	/* con1: CNSTU4 */
/* 59 */	"2",	/* con2: CNSTI4 */
/* 60 */	"2",	/* con2: CNSTU4 */
/* 61 */	"3",	/* con3: CNSTI4 */
/* 62 */	"3",	/* con3: CNSTU4 */
/* 63 */	"%0",	/* addr: base */
/* 64 */	"%0",	/* addr: baseaddr */
/* 65 */	"%1(,%0)",	/* addr: ADDI4(index,baseaddr) */
/* 66 */	"%1(,%0)",	/* addr: ADDP4(index,baseaddr) */
/* 67 */	"%1(,%0)",	/* addr: ADDU4(index,baseaddr) */
/* 68 */	"%1(%0)",	/* addr: ADDI4(reg,baseaddr) */
/* 69 */	"%1(%0)",	/* addr: ADDP4(reg,baseaddr) */
/* 70 */	"%1(%0)",	/* addr: ADDU4(reg,baseaddr) */
/* 71 */	"(%1,%0)",	/* addr: ADDI4(index,reg) */
/* 72 */	"(%1,%0)",	/* addr: ADDP4(index,reg) */
/* 73 */	"(%1,%0)",	/* addr: ADDU4(index,reg) */
/* 74 */	"(,%0)",	/* addr: index */
/* 75 */	"%0",	/* mem1: INDIRI1(addr) */
/* 76 */	"%0",	/* mem1: INDIRU1(addr) */
/* 77 */	"%0",	/* mem2: INDIRI2(addr) */
/* 78 */	"%0",	/* mem2: INDIRU2(addr) */
/* 79 */	"%0",	/* mem4: INDIRI4(addr) */
/* 80 */	"%0",	/* mem4: INDIRU4(addr) */
/* 81 */	"%0",	/* mem4: INDIRP4(addr) */
/* 82 */	"%0",	/* rc: reg */
/* 83 */	"%0",	/* rc: con */
/* 84 */	"%0",	/* mr: reg */
/* 85 */	"%0",	/* mr: mem4 */
/* 86 */	"%0",	/* mr1: reg */
/* 87 */	"%0",	/* mr1: mem1 */
/* 88 */	"%0",	/* mr2: reg */
/* 89 */	"%0",	/* mr2: mem2 */
/* 90 */	"%0",	/* mrc: mem4 */
/* 91 */	"%0",	/* mrc: mem1 */
/* 92 */	"%0",	/* mrc: mem2 */
/* 93 */	"%0",	/* mrc: rc */
/* 94 */	"leal %0,%c\n",	/* reg: addr */
/* 95 */	"movl %0,%c\n",	/* reg: mr */
/* 96 */	"movb %0,%c\n",	/* reg: mr1 */
/* 97 */	"movw %0,%c\n",	/* reg: mr2 */
/* 98 */	"movl %0,%c\n",	/* reg: con */
/* 99 */	"# move\n",	/* reg: LOADI1(reg) */
/* 100 */	"# move\n",	/* reg: LOADI2(reg) */
/* 101 */	"# move\n",	/* reg: LOADI4(reg) */
/* 102 */	"# move\n",	/* reg: LOADU1(reg) */
/* 103 */	"# move\n",	/* reg: LOADU2(reg) */
/* 104 */	"# move\n",	/* reg: LOADU4(reg) */
/* 105 */	"# move\n",	/* reg: LOADP4(reg) */
/* 106 */	"?movl %0,%c\naddl %1,%c\n",	/* reg: ADDI4(reg,mrc) */
/* 107 */	"?movl %0,%c\naddl %1,%c\n",	/* reg: ADDP4(reg,mrc) */
/* 108 */	"?movl %0,%c\naddl %1,%c\n",	/* reg: ADDU4(reg,mrc) */
/* 109 */	"?movl %0,%c\nsubl %1,%c\n",	/* reg: SUBI4(reg,mrc) */
/* 110 */	"?movl %0,%c\nsubl %1,%c\n",	/* reg: SUBP4(reg,mrc) */
/* 111 */	"?movl %0,%c\nsubl %1,%c\n",	/* reg: SUBU4(reg,mrc) */
/* 112 */	"?movl %0,%c\nandl %1,%c\n",	/* reg: BANDI4(reg,mrc) */
/* 113 */	"?movl %0,%c\norl %1,%c\n",	/* reg: BORI4(reg,mrc) */
/* 114 */	"?movl %0,%c\nxorl %1,%c\n",	/* reg: BXORI4(reg,mrc) */
/* 115 */	"?movl %0,%c\nandl %1,%c\n",	/* reg: BANDU4(reg,mrc) */
/* 116 */	"?movl %0,%c\norl %1,%c\n",	/* reg: BORU4(reg,mrc) */
/* 117 */	"?movl %0,%c\nxorl %1,%c\n",	/* reg: BXORU4(reg,mrc) */
/* 118 */	"incl %1\n",	/* stmt: ASGNI4(addr,ADDI4(mem4,con1)) */
/* 119 */	"incl %1\n",	/* stmt: ASGNI4(addr,ADDU4(mem4,con1)) */
/* 120 */	"incl %1\n",	/* stmt: ASGNP4(addr,ADDP4(mem4,con1)) */
/* 121 */	"decl %1\n",	/* stmt: ASGNI4(addr,SUBI4(mem4,con1)) */
/* 122 */	"decl %1\n",	/* stmt: ASGNI4(addr,SUBU4(mem4,con1)) */
/* 123 */	"decl %1\n",	/* stmt: ASGNP4(addr,SUBP4(mem4,con1)) */
/* 124 */	"addl %2,%1\n",	/* stmt: ASGNI4(addr,ADDI4(mem4,rc)) */
/* 125 */	"sub %2,%1\n",	/* stmt: ASGNI4(addr,SUBI4(mem4,rc)) */
/* 126 */	"add %2,%1\n",	/* stmt: ASGNU4(addr,ADDU4(mem4,rc)) */
/* 127 */	"sub %2,%1\n",	/* stmt: ASGNU4(addr,SUBU4(mem4,rc)) */
/* 128 */	"andl %2,%1\n",	/* stmt: ASGNI4(addr,BANDI4(mem4,rc)) */
/* 129 */	"orl %2,%1\n",	/* stmt: ASGNI4(addr,BORI4(mem4,rc)) */
/* 130 */	"xorl %2,%1\n",	/* stmt: ASGNI4(addr,BXORI4(mem4,rc)) */
/* 131 */	"andl %2,%1\n",	/* stmt: ASGNU4(addr,BANDU4(mem4,rc)) */
/* 132 */	"orl %2,%1\n",	/* stmt: ASGNU4(addr,BORU4(mem4,rc)) */
/* 133 */	"xorl %2,%1\n",	/* stmt: ASGNU4(addr,BXORU4(mem4,rc)) */
/* 134 */	"?movl %0,%c\nnotl %c\n",	/* reg: BCOMI4(reg) */
/* 135 */	"?movl %0,%c\nnotl %c\n",	/* reg: BCOMU4(reg) */
/* 136 */	"?movl %0,%c\nnegl %c\n",	/* reg: NEGI4(reg) */
/* 137 */	"notl %1\n",	/* stmt: ASGNI4(addr,BCOMI4(mem4)) */
/* 138 */	"notl %1\n",	/* stmt: ASGNU4(addr,BCOMU4(mem4)) */
/* 139 */	"negl %1\n",	/* stmt: ASGNI4(addr,NEGI4(mem4)) */
/* 140 */	"?movl %0,%c\nsall %1,%c\n",	/* reg: LSHI4(reg,rc5) */
/* 141 */	"?movl %0,%c\nshll %1,%c\n",	/* reg: LSHU4(reg,rc5) */
/* 142 */	"?movl %0,%c\nsarl %1,%c\n",	/* reg: RSHI4(reg,rc5) */
/* 143 */	"?movl %0,%c\nshrl %1,%c\n",	/* reg: RSHU4(reg,rc5) */
/* 144 */	"sall %2,%1\n",	/* stmt: ASGNI4(addr,LSHI4(mem4,rc5)) */
/* 145 */	"shll %2,%1\n",	/* stmt: ASGNI4(addr,LSHU4(mem4,rc5)) */
/* 146 */	"sarl %2,%1\n",	/* stmt: ASGNI4(addr,RSHI4(mem4,rc5)) */
/* 147 */	"shrl %2,%1\n",	/* stmt: ASGNI4(addr,RSHU4(mem4,rc5)) */
/* 148 */	"$%a",	/* rc5: CNSTI4 */
/* 149 */	"%%cl",	/* rc5: reg */
/* 150 */	"?movl %0,%c\nimull %1,%c\n",	/* reg: MULI4(reg,mrc) */
/* 151 */	"imul %0,%1,%c\n",	/* reg: MULI4(con,mr) */
/* 152 */	"mull %1\n",	/* reg: MULU4(reg,mr) */
/* 153 */	"xorl %%edx,%%edx\ndivl %1\n",	/* reg: DIVU4(reg,reg) */
/* 154 */	"xorl %%edx,%%edx\ndivl %1\n",	/* reg: MODU4(reg,reg) */
/* 155 */	"cdq\nidivl %1\n",	/* reg: DIVI4(reg,reg) */
/* 156 */	"cdq\nidivl %1\n",	/* reg: MODI4(reg,reg) */
/* 157 */	"movl %0,%c\n",	/* reg: CVPU4(reg) */
/* 158 */	"movl %0,%c\n",	/* reg: CVUP4(reg) */
/* 159 */	"movsbl %0,%c\n",	/* reg: CVII4(INDIRI1(addr)) */
/* 160 */	"movswl %0,%c\n",	/* reg: CVII4(INDIRI2(addr)) */
/* 161 */	"movzbl %0,%c\n",	/* reg: CVUU4(INDIRU1(addr)) */
/* 162 */	"movzwl %0,%c\n",	/* reg: CVUU4(INDIRU2(addr)) */
/* 163 */	"# extend\n",	/* reg: CVII4(reg) */
/* 164 */	"# extend\n",	/* reg: CVIU4(reg) */
/* 165 */	"# extend\n",	/* reg: CVUI4(reg) */
/* 166 */	"# extend\n",	/* reg: CVUU4(reg) */
/* 167 */	"# truncate\n",	/* reg: CVII1(reg) */
/* 168 */	"# truncate\n",	/* reg: CVII2(reg) */
/* 169 */	"# truncate\n",	/* reg: CVUU1(reg) */
/* 170 */	"# truncate\n",	/* reg: CVUU2(reg) */
/* 171 */	"%0",	/* mrca: mem4 */
/* 172 */	"%0",	/* mrca: rc */
/* 173 */	"$%a",	/* mrca: ADDRGP4 */
/* 174 */	"$%a",	/* mrca: ADDRGP8 */
/* 175 */	"movb %1,%0\n",	/* stmt: ASGNI1(addr,rc) */
/* 176 */	"movw %1,%0\n",	/* stmt: ASGNI2(addr,rc) */
/* 177 */	"movl %1,%0\n",	/* stmt: ASGNI4(addr,rc) */
/* 178 */	"movb %1,%0\n",	/* stmt: ASGNU1(addr,rc) */
/* 179 */	"movw %1,%0\n",	/* stmt: ASGNU2(addr,rc) */
/* 180 */	"movl %1,%0\n",	/* stmt: ASGNU4(addr,rc) */
/* 181 */	"movl %1,%0\n",	/* stmt: ASGNP4(addr,rc) */
/* 182 */	"pushl %0\n",	/* stmt: ARGI4(mrca) */
/* 183 */	"pushl %0\n",	/* stmt: ARGU4(mrca) */
/* 184 */	"pushl %0\n",	/* stmt: ARGP4(mrca) */
/* 185 */	"movl $%a,%%ecx\nrep\nmovsb\n",	/* stmt: ASGNB(reg,INDIRB(reg)) */
/* 186 */	"subl $%a,%%esp\nmovl %%esp,%%edi\nmovl $%a,%%ecx\nrep\nmovsb\n",	/* stmt: ARGB(INDIRB(reg)) */
/* 187 */	"l %0",	/* memf: INDIRF8(addr) */
/* 188 */	"s %0",	/* memf: INDIRF4(addr) */
/* 189 */	"s %0",	/* memf: CVFF8(INDIRF4(addr)) */
/* 190 */	"l %0",	/* memf: CVFF4(INDIRF8(addr)) */
/* 191 */	"fld%0\n",	/* freg: memf */
/* 192 */	"fstpl %0\n",	/* stmt: ASGNF8(addr,freg) */
/* 193 */	"fstps %0\n",	/* stmt: ASGNF4(addr,freg) */
/* 194 */	"fstps %0\n",	/* stmt: ASGNF4(addr,CVFF4(freg)) */
/* 195 */	"subl $8,%%esp\nfstpl (%%esp)\n",	/* stmt: ARGF8(freg) */
/* 196 */	"subl $4,%%esp\nfstps (%%esp)\n",	/* stmt: ARGF4(freg) */
/* 197 */	"fchs\n",	/* freg: NEGF8(freg) */
/* 198 */	"fchs\n",	/* freg: NEGF4(freg) */
/* 199 */	"%0",	/* flt: memf */
/* 200 */	"p %%st(1),%%st",	/* flt: freg */
/* 201 */	"fadd%1\n",	/* freg: ADDF4(freg,flt) */
/* 202 */	"fadd%1\n",	/* freg: ADDF8(freg,flt) */
/* 203 */	"fdiv%1\n",	/* freg: DIVF4(freg,flt) */
/* 204 */	"fdiv%1\n",	/* freg: DIVF8(freg,flt) */
/* 205 */	"fmul%1\n",	/* freg: MULF4(freg,flt) */
/* 206 */	"fmul%1\n",	/* freg: MULF8(freg,flt) */
/* 207 */	"fsub%1\n",	/* freg: SUBF4(freg,flt) */
/* 208 */	"fsub%1\n",	/* freg: SUBF8(freg,flt) */
/* 209 */	"# CVFF8\n",	/* freg: CVFF8(freg) */
/* 210 */	"sub $4,%%esp\nfstps (%%esp)\nflds (%%esp)\naddl $4,%%esp\n",	/* freg: CVFF4(freg) */
/* 211 */	"fistpl %0\n",	/* stmt: ASGNI4(addr,CVFI4(freg)) */
/* 212 */	"subl $4,%%esp\nfistpl 0(%%esp)\npopl %c\n",	/* reg: CVFI4(freg) */
/* 213 */	"fildl %0\n",	/* freg: CVIF8(INDIRI4(addr)) */
/* 214 */	"pushl %0\nfildl (%%esp)\naddl $4,%%esp\n",	/* freg: CVIF8(reg) */
/* 215 */	"fildl %0\n",	/* freg: CVIF4(INDIRI4(addr)) */
/* 216 */	"pushl %0\nfildl (%%esp)\naddl $4,%%esp\n",	/* freg: CVIF4(reg) */
/* 217 */	"%a",	/* addrj: ADDRGP4 */
/* 218 */	"*%0",	/* addrj: reg */
/* 219 */	"*%0",	/* addrj: mem4 */
/* 220 */	"%a:\n",	/* stmt: LABELV */
/* 221 */	"jmp %0\n",	/* stmt: JUMPV(addrj) */
/* 222 */	"cmpl %1,%0\nje %a\n",	/* stmt: EQI4(mem4,rc) */
/* 223 */	"cmpl %1,%0\njge %a\n",	/* stmt: GEI4(mem4,rc) */
/* 224 */	"cmpl %1,%0\njg %a\n",	/* stmt: GTI4(mem4,rc) */
/* 225 */	"cmpl %1,%0\njle %a\n",	/* stmt: LEI4(mem4,rc) */
/* 226 */	"cmpl %1,%0\njl %a\n",	/* stmt: LTI4(mem4,rc) */
/* 227 */	"cmpl %1,%0\njne %a\n",	/* stmt: NEI4(mem4,rc) */
/* 228 */	"cmpl %1,%0\njae %a\n",	/* stmt: GEU4(mem4,rc) */
/* 229 */	"cmpl %1,%0\nja  %a\n",	/* stmt: GTU4(mem4,rc) */
/* 230 */	"cmpl %1,%0\njbe %a\n",	/* stmt: LEU4(mem4,rc) */
/* 231 */	"cmpl %1,%0\njb  %a\n",	/* stmt: LTU4(mem4,rc) */
/* 232 */	"cmpl %1,%0\nje %a\n",	/* stmt: EQI4(reg,mrc) */
/* 233 */	"cmpl %1,%0\njge %a\n",	/* stmt: GEI4(reg,mrc) */
/* 234 */	"cmpl %1,%0\njg %a\n",	/* stmt: GTI4(reg,mrc) */
/* 235 */	"cmpl %1,%0\njle %a\n",	/* stmt: LEI4(reg,mrc) */
/* 236 */	"cmpl %1,%0\njl %a\n",	/* stmt: LTI4(reg,mrc) */
/* 237 */	"cmpl %1,%0\njne %a\n",	/* stmt: NEI4(reg,mrc) */
/* 238 */	"cmpl %1,%0\nje %a\n",	/* stmt: EQU4(reg,mrc) */
/* 239 */	"cmpl %1,%0\njae %a\n",	/* stmt: GEU4(reg,mrc) */
/* 240 */	"cmpl %1,%0\nja %a\n",	/* stmt: GTU4(reg,mrc) */
/* 241 */	"cmpl %1,%0\njbe %a\n",	/* stmt: LEU4(reg,mrc) */
/* 242 */	"cmpl %1,%0\njb %a\n",	/* stmt: LTU4(reg,mrc) */
/* 243 */	"cmpl %1,%0\njne %a\n",	/* stmt: NEU4(reg,mrc) */
/* 244 */	"testl %1,%0\nje %a\n",	/* stmt: EQI4(BANDU4(mr,con),con0) */
/* 245 */	"testl %1,%0\njne %a\n",	/* stmt: NEI4(BANDU4(mr,con),con0) */
/* 246 */	"testw %1,%0\nje %a\n",	/* stmt: EQI4(BANDU4(CVII2(INDIRI2(addr)),con),con0) */
/* 247 */	"testw %1,%0\njne %a\n",	/* stmt: NEI4(BANDU4(CVII2(INDIRI2(addr)),con),con0) */
/* 248 */	"testw %1,%0\nje %a\n",	/* stmt: EQI4(BANDU4(CVIU2(INDIRI2(addr)),con),con0) */
/* 249 */	"testw %1,%0\njne %a\n",	/* stmt: NEI4(BANDU4(CVIU2(INDIRI2(addr)),con),con0) */
/* 250 */	"testb %1,%0\nje %a\n",	/* stmt: EQI4(BANDU4(CVII1(INDIRI1(addr)),con),con0) */
/* 251 */	"l %0",	/* cmpf: INDIRF8(addr) */
/* 252 */	"s %0",	/* cmpf: INDIRF4(addr) */
/* 253 */	"s %0",	/* cmpf: CVFF8(INDIRF4(addr)) */
/* 254 */	"p",	/* cmpf: freg */
/* 255 */	"fcomp%0\nfstsw %%ax\nsahf\nje %a\n",	/* stmt: EQF8(cmpf,freg) */
/* 256 */	"fcomp%0\nfstsw %%ax\nsahf\njbe %a\n",	/* stmt: GEF8(cmpf,freg) */
/* 257 */	"fcomp%0\nfstsw %%ax\nsahf\njb %a\n",	/* stmt: GTF8(cmpf,freg) */
/* 258 */	"fcomp%0\nfstsw %%ax\nsahf\njae %a\n",	/* stmt: LEF8(cmpf,freg) */
/* 259 */	"fcomp%0\nfstsw %%ax\nsahf\nja %a\n",	/* stmt: LTF8(cmpf,freg) */
/* 260 */	"fcomp%0\nfstsw %%ax\nsahf\njne %a\n",	/* stmt: NEF8(cmpf,freg) */
/* 261 */	"fcomp%0\nfstsw %%ax\nsahf\nje %a\n",	/* stmt: EQF4(cmpf,freg) */
/* 262 */	"fcomp%0\nfstsw %%ax\nsahf\njbe %a\n",	/* stmt: GEF4(cmpf,freg) */
/* 263 */	"fcomp%0\nfstsw %%ax\nsahf\njb %a\n",	/* stmt: GTF4(cmpf,freg) */
/* 264 */	"fcomp%0\nfstsw %%ax\nsahf\njae %a\n",	/* stmt: LEF4(cmpf,freg) */
/* 265 */	"fcomp%0\nfstsw %%ax\nsahf\nja %a\n",	/* stmt: LTF4(cmpf,freg) */
/* 266 */	"fcomp%0\nfstsw %%ax\nsahf\njne %a\n",	/* stmt: NEF4(cmpf,freg) */
/* 267 */	"fidivl %1\n",	/* freg: DIVF8(freg,CVIF8(INDIRI4(addr))) */
/* 268 */	"fidivrl %0\n",	/* freg: DIVF8(CVIF8(INDIRI4(addr)),freg) */
/* 269 */	"fidivs %1\n",	/* freg: DIVF8(freg,CVIF8(CVII2(INDIRI2(addr)))) */
/* 270 */	"fidivrs %0\n",	/* freg: DIVF8(CVIF8(CVII2(INDIRI2(addr))),freg) */
/* 271 */	"fimull %1\n",	/* freg: MULF8(freg,CVIF8(INDIRI4(addr))) */
/* 272 */	"fimuls %1\n",	/* freg: MULF8(freg,CVIF8(CVII2(INDIRI2(addr)))) */
/* 273 */	"fisubl %1\n",	/* freg: SUBF8(freg,CVIF8(INDIRI4(addr))) */
/* 274 */	"fisubrl %0\n",	/* freg: SUBF8(CVIF8(INDIRI4(addr)),freg) */
/* 275 */	"fisubs %1\n",	/* freg: SUBF8(freg,CVIF8(CVII2(INDIRI2(addr)))) */
/* 276 */	"fisubrs %0\n",	/* freg: SUBF8(CVIF8(CVII2(INDIRI2(addr))),freg) */
/* 277 */	"fiaddl %1\n",	/* freg: ADDF8(freg,CVIF8(INDIRI4(addr))) */
/* 278 */	"fiadds %1\n",	/* freg: ADDF8(freg,CVIF8(CVII2(INDIRI2(addr)))) */
/* 279 */	"fdivs %1\n",	/* freg: ADDF8(freg,CVFF8(INDIRF4(addr))) */
/* 280 */	"fsubs %1\n",	/* freg: SUBF8(freg,CVFF8(INDIRF4(addr))) */
/* 281 */	"fmuls %1\n",	/* freg: MULF8(freg,CVFF8(INDIRF4(addr))) */
/* 282 */	"fdivs %1\n",	/* freg: DIVF8(freg,CVFF8(INDIRF4(addr))) */
/* 283 */	"fld%0\n",	/* freg: LOADF8(memf) */
/* 284 */	"call %0\naddl $%a,%%esp\n",	/* reg: CALLI4(addrj) */
/* 285 */	"call %0\naddl $%a,%%esp\n",	/* reg: CALLU4(addrj) */
/* 286 */	"call %0\naddl $%a,%%esp\n",	/* reg: CALLP4(addrj) */
/* 287 */	"call %0\n",	/* reg: CALLI4(addrj) */
/* 288 */	"call %0\n",	/* reg: CALLU4(addrj) */
/* 289 */	"call %0\n",	/* reg: CALLP4(addrj) */
/* 290 */	"call %0\naddl $%a,%%esp\n",	/* stmt: CALLV(addrj) */
/* 291 */	"call %0\n",	/* stmt: CALLV(addrj) */
/* 292 */	"call %0\naddl $%a,%%esp\n",	/* freg: CALLF4(addrj) */
/* 293 */	"call %0\n",	/* freg: CALLF4(addrj) */
/* 294 */	"call %0\naddl $%a,%%esp\nfstp %%st(0)\n",	/* stmt: CALLF4(addrj) */
/* 295 */	"call %0\nfstp %%st(0)\n",	/* stmt: CALLF4(addrj) */
/* 296 */	"call %0\naddl $%a,%%esp\n",	/* freg: CALLF8(addrj) */
/* 297 */	"call %0\n",	/* freg: CALLF8(addrj) */
/* 298 */	"call %0\naddl $%a,%%esp\nfstp %%st(0)\n",	/* stmt: CALLF8(addrj) */
/* 299 */	"call %0\nfstp %%st(0)\n",	/* stmt: CALLF8(addrj) */
/* 300 */	"# ret\n",	/* stmt: RETI4(reg) */
/* 301 */	"# ret\n",	/* stmt: RETU4(reg) */
/* 302 */	"# ret\n",	/* stmt: RETP4(reg) */
/* 303 */	"# ret\n",	/* stmt: RETF4(freg) */
/* 304 */	"# ret\n",	/* stmt: RETF8(freg) */
};

static char _isinstruction[] = {
/* 0 */	0,
/* 1 */	1,	/* # read register\n */
/* 2 */	1,	/* # read register\n */
/* 3 */	1,	/* # read register\n */
/* 4 */	1,	/* # read register\n */
/* 5 */	1,	/* # read register\n */
/* 6 */	1,	/* # read register\n */
/* 7 */	1,	/* # read register\n */
/* 8 */	1,	/* # read register\n */
/* 9 */	1,	/* # read register\n */
/* 10 */	1,	/* # read register\n */
/* 11 */	1,	/* # read register\n */
/* 12 */	1,	/* # read register\n */
/* 13 */	1,	/* # write register\n */
/* 14 */	1,	/* # write register\n */
/* 15 */	1,	/* # write register\n */
/* 16 */	1,	/* # write register\n */
/* 17 */	1,	/* # write register\n */
/* 18 */	1,	/* # write register\n */
/* 19 */	1,	/* # write register\n */
/* 20 */	1,	/* # write register\n */
/* 21 */	1,	/* # write register\n */
/* 22 */	1,	/* # write register\n */
/* 23 */	1,	/* # write register\n */
/* 24 */	1,	/* # write register\n */
/* 25 */	0,	/* %a */
/* 26 */	0,	/* %a */
/* 27 */	0,	/* %a */
/* 28 */	0,	/* %a */
/* 29 */	0,	/* %a */
/* 30 */	0,	/* %a */
/* 31 */	0,	/* %a */
/* 32 */	0,	/* %a */
/* 33 */	0,	/* %a */
/* 34 */	0,	/* %a */
/* 35 */	0,	/* $%0 */
/* 36 */	0,	/*  */
/* 37 */	0,	/*  */
/* 38 */	0,	/* %a */
/* 39 */	0,	/* %a */
/* 40 */	0,	/* %0 */
/* 41 */	0,	/* %a */
/* 42 */	0,	/* (%0) */
/* 43 */	0,	/* %1(%0) */
/* 44 */	0,	/* %1(%0) */
/* 45 */	0,	/* %1(%0) */
/* 46 */	0,	/* %a(%%ebp) */
/* 47 */	0,	/* %a(%%ebp) */
/* 48 */	0,	/* %0 */
/* 49 */	0,	/* %0,2 */
/* 50 */	0,	/* %0,4 */
/* 51 */	0,	/* %0,8 */
/* 52 */	0,	/* %0,2 */
/* 53 */	0,	/* %0,4 */
/* 54 */	0,	/* %0,8 */
/* 55 */	0,	/* 1 */
/* 56 */	0,	/* 1 */
/* 57 */	0,	/* 1 */
/* 58 */	0,	/* 1 */
/* 59 */	0,	/* 2 */
/* 60 */	0,	/* 2 */
/* 61 */	0,	/* 3 */
/* 62 */	0,	/* 3 */
/* 63 */	0,	/* %0 */
/* 64 */	0,	/* %0 */
/* 65 */	0,	/* %1(,%0) */
/* 66 */	0,	/* %1(,%0) */
/* 67 */	0,	/* %1(,%0) */
/* 68 */	0,	/* %1(%0) */
/* 69 */	0,	/* %1(%0) */
/* 70 */	0,	/* %1(%0) */
/* 71 */	0,	/* (%1,%0) */
/* 72 */	0,	/* (%1,%0) */
/* 73 */	0,	/* (%1,%0) */
/* 74 */	0,	/* (,%0) */
/* 75 */	0,	/* %0 */
/* 76 */	0,	/* %0 */
/* 77 */	0,	/* %0 */
/* 78 */	0,	/* %0 */
/* 79 */	0,	/* %0 */
/* 80 */	0,	/* %0 */
/* 81 */	0,	/* %0 */
/* 82 */	0,	/* %0 */
/* 83 */	0,	/* %0 */
/* 84 */	0,	/* %0 */
/* 85 */	0,	/* %0 */
/* 86 */	0,	/* %0 */
/* 87 */	0,	/* %0 */
/* 88 */	0,	/* %0 */
/* 89 */	0,	/* %0 */
/* 90 */	0,	/* %0 */
/* 91 */	0,	/* %0 */
/* 92 */	0,	/* %0 */
/* 93 */	0,	/* %0 */
/* 94 */	1,	/* leal %0,%c\n */
/* 95 */	1,	/* movl %0,%c\n */
/* 96 */	1,	/* movb %0,%c\n */
/* 97 */	1,	/* movw %0,%c\n */
/* 98 */	1,	/* movl %0,%c\n */
/* 99 */	1,	/* # move\n */
/* 100 */	1,	/* # move\n */
/* 101 */	1,	/* # move\n */
/* 102 */	1,	/* # move\n */
/* 103 */	1,	/* # move\n */
/* 104 */	1,	/* # move\n */
/* 105 */	1,	/* # move\n */
/* 106 */	1,	/* ?movl %0,%c\naddl %1,%c\n */
/* 107 */	1,	/* ?movl %0,%c\naddl %1,%c\n */
/* 108 */	1,	/* ?movl %0,%c\naddl %1,%c\n */
/* 109 */	1,	/* ?movl %0,%c\nsubl %1,%c\n */
/* 110 */	1,	/* ?movl %0,%c\nsubl %1,%c\n */
/* 111 */	1,	/* ?movl %0,%c\nsubl %1,%c\n */
/* 112 */	1,	/* ?movl %0,%c\nandl %1,%c\n */
/* 113 */	1,	/* ?movl %0,%c\norl %1,%c\n */
/* 114 */	1,	/* ?movl %0,%c\nxorl %1,%c\n */
/* 115 */	1,	/* ?movl %0,%c\nandl %1,%c\n */
/* 116 */	1,	/* ?movl %0,%c\norl %1,%c\n */
/* 117 */	1,	/* ?movl %0,%c\nxorl %1,%c\n */
/* 118 */	1,	/* incl %1\n */
/* 119 */	1,	/* incl %1\n */
/* 120 */	1,	/* incl %1\n */
/* 121 */	1,	/* decl %1\n */
/* 122 */	1,	/* decl %1\n */
/* 123 */	1,	/* decl %1\n */
/* 124 */	1,	/* addl %2,%1\n */
/* 125 */	1,	/* sub %2,%1\n */
/* 126 */	1,	/* add %2,%1\n */
/* 127 */	1,	/* sub %2,%1\n */
/* 128 */	1,	/* andl %2,%1\n */
/* 129 */	1,	/* orl %2,%1\n */
/* 130 */	1,	/* xorl %2,%1\n */
/* 131 */	1,	/* andl %2,%1\n */
/* 132 */	1,	/* orl %2,%1\n */
/* 133 */	1,	/* xorl %2,%1\n */
/* 134 */	1,	/* ?movl %0,%c\nnotl %c\n */
/* 135 */	1,	/* ?movl %0,%c\nnotl %c\n */
/* 136 */	1,	/* ?movl %0,%c\nnegl %c\n */
/* 137 */	1,	/* notl %1\n */
/* 138 */	1,	/* notl %1\n */
/* 139 */	1,	/* negl %1\n */
/* 140 */	1,	/* ?movl %0,%c\nsall %1,%c\n */
/* 141 */	1,	/* ?movl %0,%c\nshll %1,%c\n */
/* 142 */	1,	/* ?movl %0,%c\nsarl %1,%c\n */
/* 143 */	1,	/* ?movl %0,%c\nshrl %1,%c\n */
/* 144 */	1,	/* sall %2,%1\n */
/* 145 */	1,	/* shll %2,%1\n */
/* 146 */	1,	/* sarl %2,%1\n */
/* 147 */	1,	/* shrl %2,%1\n */
/* 148 */	0,	/* $%a */
/* 149 */	0,	/* %%cl */
/* 150 */	1,	/* ?movl %0,%c\nimull %1,%c\n */
/* 151 */	1,	/* imul %0,%1,%c\n */