i370-opc.c

基于4个mips核的noc设计

}

static i370_insn_t
insert_ss_d2 (insn, value, errmsg)
     i370_insn_t insn;
     long value;
     const char **errmsg;
{
  insn.i[1] |= (value & 0xfff) << 16;
  return insn;
}

static i370_insn_t
insert_rxf_r3 (insn, value, errmsg)
     i370_insn_t insn;
     long value;
     const char **errmsg;
{
  insn.i[1] |= (value & 0xf) << 28;
  return insn;
}

static long
extract_ss_b2 (insn, invalid)
     i370_insn_t insn;
     int *invalid;
{
  return (insn.i[1] >>28) & 0xf;
}

static long
extract_ss_d2 (insn, invalid)
     i370_insn_t insn;
     int *invalid;
{
  return (insn.i[1] >>16) & 0xfff;
}

static long
extract_rxf_r3 (insn, invalid)
     i370_insn_t insn;
     int *invalid;
{
  return (insn.i[1] >>28) & 0xf;
}


/* Macros used to form opcodes.  */

/* The short-instruction opcode.  */
#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8)
#define OPS_MASK OPS (0xff)

/* the extended instruction opcode */
#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24)
#define XOPS_MASK XOPS (0xff)

/* the S instruction opcode */
#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16)
#define SOPS_MASK SOPS (0xffff)

/* the E instruction opcode */
#define EOPS(x) (((unsigned short)(x)) & 0xffff)
#define EOPS_MASK EOPS (0xffff)

/* the RI instruction opcode */
#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \
                 ((((unsigned short)(x)) & 0x00f) << 16))
#define ROPS_MASK ROPS (0xfff)

/* --------------------------------------------------------- */
/* An E form instruction.  */
#define E(op)  (EOPS (op))
#define E_MASK E (0xffff)

/* An RR form instruction.  */
#define RR(op, r1, r2) \
  (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \
              ((((unsigned short)(r2)) & 0xf) ))

#define RR_MASK RR (0xff, 0x0, 0x0)

/* An SVC-style instruction.  */
#define SVC(op, i) \
  (OPS (op) | (((unsigned short)(i)) & 0xff))

#define SVC_MASK SVC (0xff, 0x0)

/* An RRE form instruction.  */
#define RRE(op, r1, r2) \
  (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) |   \
               ((((unsigned short)(r2)) & 0xf) ))

#define RRE_MASK RRE (0xffff, 0x0, 0x0)

/* An RRF form instruction.  */
#define RRF(op, r3, r1, r2) \
  (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) |   \
               ((((unsigned short)(r1)) & 0xf) << 4)  |   \
               ((((unsigned short)(r2)) & 0xf) ))

#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)

/* An RX form instruction. */
#define RX(op, r1, x2, b2, d2) \
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
              ((((unsigned short)(x2)) & 0xf) << 16) |  \
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
              ((((unsigned short)(d2)) & 0xfff)))

#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)

/* An RXE form instruction high word. */
#define RXEH(op, r1, x2, b2, d2) \
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
              ((((unsigned short)(x2)) & 0xf) << 16) |  \
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
              ((((unsigned short)(d2)) & 0xfff)))

#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)

/* An RXE form instruction low word. */
#define RXEL(op) \
              ((((unsigned short)(op)) & 0xff) << 16 )

#define RXEL_MASK RXEL (0xff)

/* An RXF form instruction high word. */
#define RXFH(op, r1, x2, b2, d2) \
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
              ((((unsigned short)(x2)) & 0xf) << 16) |  \
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
              ((((unsigned short)(d2)) & 0xfff)))

#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)

/* An RXF form instruction low word. */
#define RXFL(op, r3) \
              (((((unsigned short)(r3)) & 0xf)  << 28 ) | \
               ((((unsigned short)(op)) & 0xff) << 16 ))

#define RXFL_MASK RXFL (0xff, 0)

/* An RS form instruction. */
#define RS(op, r1, b3, b2, d2) \
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
              ((((unsigned short)(b3)) & 0xf) << 16) |  \
              ((((unsigned short)(b2)) & 0xf) << 12) |  \
              ((((unsigned short)(d2)) & 0xfff)))

#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)

/* An RSI form instruction. */
#define RSI(op, r1, r3, i2) \
  (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
              ((((unsigned short)(r3)) & 0xf) << 16) |  \
              ((((unsigned short)(i2)) & 0xffff)))

#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)

/* An RI form instruction. */
#define RI(op, r1, i2) \
  (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) |  \
              ((((unsigned short)(i2)) & 0xffff)))

#define RI_MASK RI (0xfff, 0x0, 0x0)

/* An SI form instruction. */
#define SI(op, i2, b1, d1) \
  (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) |  \
              ((((unsigned short)(b1)) & 0xf)  << 12) |  \
              ((((unsigned short)(d1)) & 0xfff)))

#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)

/* An S form instruction. */
#define S(op, b2, d2) \
  (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) |  \
              ((((unsigned short)(d2)) & 0xfff)))

#define S_MASK S (0xffff, 0x0, 0x0)

/* An SS form instruction high word. */
#define SSH(op, l, b1, d1) \
  (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) |  \
              ((((unsigned short)(b1)) & 0xf)  << 12) |  \
              ((((unsigned short)(d1)) & 0xfff)))

/* An SS form instruction low word. */
#define SSL(b2, d2) \
            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \
              ((((unsigned short)(d1)) & 0xfff) << 16 ))

#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)

/* An SSE form instruction high word. */
#define SSEH(op, b1, d1) \
  (SOPS(op) | ((((unsigned short)(b1)) & 0xf)  << 12) |  \
              ((((unsigned short)(d1)) & 0xfff)))

/* An SSE form instruction low word. */
#define SSEL(b2, d2) \
            ( ((((unsigned short)(b1)) & 0xf)   << 28) |  \
              ((((unsigned short)(d1)) & 0xfff) << 16 ))

#define SSE_MASK SSEH (0xffff, 0x0, 0x0)


/* Smaller names for the flags so each entry in the opcodes table will
   fit on a single line.  These flags are set up so that e.g. IXA means
   the insn is supported on the 370/XA or newer architecture.
   Note that 370 or older obsolete insn's are not supported ...
 */
#define	IBF	I370_OPCODE_ESA390_BF
#define	IBS	I370_OPCODE_ESA390_BS
#define	ICK	I370_OPCODE_ESA390_CK
#define	ICM	I370_OPCODE_ESA390_CM
#define	IFX	I370_OPCODE_ESA390_FX
#define	IHX	I370_OPCODE_ESA390_HX
#define	IIR	I370_OPCODE_ESA390_IR
#define	IMI	I370_OPCODE_ESA390_MI
#define	IPC	I370_OPCODE_ESA390_PC
#define	IPL	I370_OPCODE_ESA390_PL
#define	IQR	I370_OPCODE_ESA390_QR
#define	IRP	I370_OPCODE_ESA390_RP
#define	ISA	I370_OPCODE_ESA390_SA
#define	ISG	I370_OPCODE_ESA390_SG
#define	ISR	I370_OPCODE_ESA390_SR
#define	ITR	I370_OPCODE_ESA390_SR
#define	I390	IBF  | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
#define	IESA	I390 | I370_OPCODE_ESA370
#define IXA	IESA | I370_OPCODE_370_XA
#define	I370	IXA  | I370_OPCODE_370
#define I360	I370 | I370_OPCODE_360


/* The opcode table.

   The format of the opcode table is: