ia64-asmtab.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,903 行 · 第 1/5 页

/* This file is automatically generated by ia64-gen.  Do not edit! */
static const char *ia64_strings[] = {
  "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and",
  "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call",
  "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1",
  "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1",
  "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit",
  "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm",
  "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4",
  "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin",
  "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for",
  "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax",
  "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma",
  "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc",
  "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge",
  "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc",
  "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe",
  "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs",
  "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2",
  "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt",
  "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz",
  "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1",
  "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1",
  "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe",
  "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2",
  "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi",
  "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf",
  "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt",
  "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8",
  "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync",
  "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc",
  "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w",
  "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma",
  "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4",
};

static const struct ia64_dependency
dependencies[] = {
  { "ALAT", 0, 0, 0, -1, NULL, },
  { "AR[BSP]", 26, 0, 2, 17, NULL, },
  { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, },
  { "AR[CCV]", 26, 0, 2, 32, NULL, },
  { "AR[EC]", 26, 0, 2, 66, NULL, },
  { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].traps", 30, 0, 2, -1, NULL, },
  { "AR[FPSR].rv", 30, 0, 2, -1, NULL, },
  { "AR[ITC]", 26, 0, 2, 44, NULL, },
  { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, },
  { "AR[LC]", 26, 0, 2, 65, NULL, },
  { "AR[PFS]", 26, 0, 2, 64, NULL, },
  { "AR[PFS]", 26, 0, 2, 64, NULL, },
  { "AR[PFS]", 26, 0, 0, 64, NULL, },
  { "AR[RNAT]", 26, 0, 2, 19, NULL, },
  { "AR[RSC]", 26, 0, 2, 16, NULL, },
  { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, },
  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, },
  { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 2, -1, NULL, },
  { "CFM", 6, 0, 0, -1, NULL, },
  { "CPUID#", 7, 0, 5, -1, NULL, },
  { "CR[CMCV]", 27, 0, 3, 74, NULL, },
  { "CR[DCR]", 27, 0, 3, 0, NULL, },
  { "CR[EOI]", 27, 0, 7, 67, "SC Section 10.8.3.4", },
  { "CR[GPTA]", 27, 0, 3, 9, NULL, },
  { "CR[IFA]", 27, 0, 1, 20, NULL, },
  { "CR[IFA]", 27, 0, 3, 20, NULL, },
  { "CR[IFS]", 27, 0, 3, 23, NULL, },
  { "CR[IFS]", 27, 0, 1, 23, NULL, },
  { "CR[IFS]", 27, 0, 1, 23, NULL, },
  { "CR[IHA]", 27, 0, 3, 25, NULL, },
  { "CR[IIM]", 27, 0, 3, 24, NULL, },
  { "CR[IIP]", 27, 0, 3, 19, NULL, },
  { "CR[IIP]", 27, 0, 1, 19, NULL, },
  { "CR[IIPA]", 27, 0, 3, 22, NULL, },
  { "CR[IPSR]", 27, 0, 3, 16, NULL, },
  { "CR[IPSR]", 27, 0, 1, 16, NULL, },
  { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, },
  { "CR[ISR]", 27, 0, 3, 17, NULL, },
  { "CR[ITIR]", 27, 0, 3, 21, NULL, },
  { "CR[ITIR]", 27, 0, 1, 21, NULL, },
  { "CR[ITM]", 27, 0, 3, 1, NULL, },
  { "CR[ITV]", 27, 0, 3, 72, NULL, },
  { "CR[IVA]", 27, 0, 4, 2, NULL, },
  { "CR[IVR]", 27, 0, 7, 65, "SC Section 10.8.3.2", },
  { "CR[LID]", 27, 0, 7, 64, "SC Section 10.8.3.1", },
  { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, },
  { "CR[PMV]", 27, 0, 3, 73, NULL, },
  { "CR[PTA]", 27, 0, 3, 8, NULL, },
  { "CR[TPR]", 27, 0, 3, 66, NULL, },
  { "CR[TPR]", 27, 0, 7, 66, "SC Section 10.8.3.3", },
  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, },
  { "DBR#", 11, 0, 2, -1, NULL, },
  { "DBR#", 11, 0, 3, -1, NULL, },
  { "DTC", 0, 0, 3, -1, NULL, },
  { "DTC", 0, 0, 2, -1, NULL, },
  { "DTC", 0, 0, 0, -1, NULL, },
  { "DTC", 0, 0, 2, -1, NULL, },
  { "DTC_LIMIT*", 0, 0, 2, -1, NULL, },
  { "DTR", 0, 0, 3, -1, NULL, },
  { "DTR", 0, 0, 2, -1, NULL, },
  { "DTR", 0, 0, 3, -1, NULL, },
  { "DTR", 0, 0, 0, -1, NULL, },
  { "DTR", 0, 0, 2, -1, NULL, },
  { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, },
  { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, },
  { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, },
  { "GR0", 14, 0, 0, -1, NULL, },
  { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, },
  { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, },
  { "IBR#", 16, 0, 2, -1, NULL, },
  { "InService*", 17, 0, 3, -1, NULL, },
  { "InService*", 17, 0, 2, -1, NULL, },
  { "InService*", 17, 0, 2, -1, NULL, },
  { "IP", 0, 0, 0, -1, NULL, },
  { "ITC", 0, 0, 4, -1, NULL, },
  { "ITC", 0, 0, 2, -1, NULL, },
  { "ITC", 0, 0, 0, -1, NULL, },
  { "ITC", 0, 0, 4, -1, NULL, },
  { "ITC", 0, 0, 2, -1, NULL, },
  { "ITC_LIMIT*", 0, 0, 2, -1, NULL, },
  { "ITR", 0, 0, 2, -1, NULL, },
  { "ITR", 0, 0, 4, -1, NULL, },
  { "ITR", 0, 0, 2, -1, NULL, },
  { "ITR", 0, 0, 0, -1, NULL, },
  { "ITR", 0, 0, 4, -1, NULL, },
  { "memory", 0, 0, 0, -1, NULL, },
  { "MSR#", 18, 0, 5, -1, NULL, },
  { "PKR#", 19, 0, 3, -1, NULL, },
  { "PKR#", 19, 0, 0, -1, NULL, },
  { "PKR#", 19, 0, 2, -1, NULL, },
  { "PKR#", 19, 0, 2, -1, NULL, },
  { "PMC#", 20, 0, 2, -1, NULL, },
  { "PMC#", 20, 0, 7, -1, "SC+3 Section 12.1.1", },
  { "PMD#", 21, 0, 2, -1, NULL, },
  { "PR0", 0, 0, 0, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, },
  { "PR63", 24, 0, 2, -1, NULL, },
  { "PR63", 24, 0, 2, -1, NULL, },
  { "PR63", 24, 0, 0, -1, NULL, },
  { "PSR.ac", 28, 0, 1, 3, NULL, },
  { "PSR.ac", 28, 0, 3, 3, NULL, },
  { "PSR.ac", 28, 0, 2, 3, NULL, },
  { "PSR.be", 28, 0, 1, 1, NULL, },
  { "PSR.be", 28, 0, 3, 1, NULL, },
  { "PSR.be", 28, 0, 2, 1, NULL, },
  { "PSR.bn", 28, 0, 2, 44, NULL, },
  { "PSR.cpl", 28, 0, 1, 32, NULL, },
  { "PSR.da", 28, 0, 3, 38, NULL, },
  { "PSR.db", 28, 0, 3, 24, NULL, },
  { "PSR.db", 28, 0, 2, 24, NULL, },
  { "PSR.db", 28, 0, 3, 24, NULL, },
  { "PSR.dd", 28, 0, 3, 39, NULL, },
  { "PSR.dfh", 28, 0, 3, 19, NULL, },
  { "PSR.dfh", 28, 0, 2, 19, NULL, },
  { "PSR.dfl", 28, 0, 3, 18, NULL, },
  { "PSR.dfl", 28, 0, 2, 18, NULL, },
  { "PSR.di", 28, 0, 3, 22, NULL, },
  { "PSR.di", 28, 0, 2, 22, NULL, },
  { "PSR.dt", 28, 0, 3, 17, NULL, },
  { "PSR.dt", 28, 0, 2, 17, NULL, },
  { "PSR.ed", 28, 0, 3, 43, NULL, },
  { "PSR.i", 28, 0, 2, 14, NULL, },
  { "PSR.i", 28, 0, 3, 14, NULL, },
  { "PSR.ia", 28, 0, 0, 14, NULL, },
  { "PSR.ic", 28, 0, 2, 13, NULL, },
  { "PSR.ic", 28, 0, 3, 13, NULL, },
  { "PSR.id", 28, 0, 0, 14, NULL, },
  { "PSR.is", 28, 0, 0, 14, NULL, },
  { "PSR.it", 28, 0, 3, 14, NULL, },
  { "PSR.lp", 28, 0, 2, 25, NULL, },
  { "PSR.lp", 28, 0, 3, 25, NULL, },
  { "PSR.lp", 28, 0, 3, 25, NULL, },
  { "PSR.mc", 28, 0, 0, 35, NULL, },
  { "PSR.mfh", 28, 0, 2, 5, NULL, },
  { "PSR.mfl", 28, 0, 2, 4, NULL, },
  { "PSR.pk", 28, 0, 3, 15, NULL, },
  { "PSR.pk", 28, 0, 2, 15, NULL, },
  { "PSR.pp", 28, 0, 2, 21, NULL, },
  { "PSR.ri", 28, 0, 0, 41, NULL, },
  { "PSR.rt", 28, 0, 2, 27, NULL, },
  { "PSR.rt", 28, 0, 3, 27, NULL, },
  { "PSR.rt", 28, 0, 3, 27, NULL, },
  { "PSR.si", 28, 0, 2, 23, NULL, },
  { "PSR.si", 28, 0, 3, 23, NULL, },
  { "PSR.sp", 28, 0, 2, 20, NULL, },
  { "PSR.sp", 28, 0, 3, 20, NULL, },
  { "PSR.ss", 28, 0, 3, 40, NULL, },
  { "PSR.tb", 28, 0, 3, 26, NULL, },
  { "PSR.tb", 28, 0, 2, 26, NULL, },
  { "PSR.up", 28, 0, 2, 2, NULL, },
  { "RR#", 25, 0, 3, -1, NULL, },
  { "RR#", 25, 0, 2, -1, NULL, },
  { "RSE", 29, 0, 2, -1, NULL, },
  { "ALAT", 0, 1, 0, -1, NULL, },
  { "AR[BSP]", 26, 1, 2, 17, NULL, },
  { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, },
  { "AR[CCV]", 26, 1, 2, 32, NULL, },
  { "AR[EC]", 26, 1, 2, 66, NULL, },
  { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, },
  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, },
  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, },
  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, },
  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].rv", 30, 1, 2, -1, NULL, },
  { "AR[FPSR].traps", 30, 1, 2, -1, NULL, },
  { "AR[ITC]", 26, 1, 2, 44, NULL, },
  { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, },
  { "AR[LC]", 26, 1, 2, 65, NULL, },
  { "AR[PFS]", 26, 1, 0, 64, NULL, },
  { "AR[PFS]", 26, 1, 2, 64, NULL, },
  { "AR[PFS]", 26, 1, 2, 64, NULL, },
  { "AR[RNAT]", 26, 1, 2, 19, NULL, },
  { "AR[RSC]", 26, 1, 2, 16, NULL, },
  { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, },
  { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, },
  { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, },
  { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, },
  { "CFM", 6, 1, 2, -1, NULL, },
  { "CPUID#", 7, 1, 0, -1, NULL, },
  { "CR[CMCV]", 27, 1, 2, 74, NULL, },
  { "CR[DCR]", 27, 1, 2, 0, NULL, },
  { "CR[EOI]", 27, 1, 7, 67, "SC Section 10.8.3.4", },
  { "CR[GPTA]", 27, 1, 2, 9, NULL, },
  { "CR[IFA]", 27, 1, 2, 20, NULL, },
  { "CR[IFS]", 27, 1, 2, 23, NULL, },
  { "CR[IHA]", 27, 1, 2, 25, NULL, },
  { "CR[IIM]", 27, 1, 2, 24, NULL, },
  { "CR[IIP]", 27, 1, 2, 19, NULL, },
  { "CR[IIPA]", 27, 1, 2, 22, NULL, },
  { "CR[IPSR]", 27, 1, 2, 16, NULL, },
  { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, },
  { "CR[ISR]", 27, 1, 2, 17, NULL, },
  { "CR[ITIR]", 27, 1, 2, 21, NULL, },
  { "CR[ITM]", 27, 1, 2, 1, NULL, },
  { "CR[ITV]", 27, 1, 2, 72, NULL, },
  { "CR[IVA]", 27, 1, 2, 2, NULL, },
  { "CR[IVR]", 27, 1, 7, 65, "SC", },
  { "CR[LID]", 27, 1, 7, 64, "SC", },
  { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, },
  { "CR[PMV]", 27, 1, 2, 73, NULL, },
  { "CR[PTA]", 27, 1, 2, 8, NULL, },
  { "CR[TPR]", 27, 1, 2, 66, NULL, },
  { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, },
  { "DBR#", 11, 1, 2, -1, NULL, },
  { "DTC", 0, 1, 0, -1, NULL, },
  { "DTC", 0, 1, 2, -1, NULL, },
  { "DTC", 0, 1, 2, -1, NULL, },
  { "DTC_LIMIT*", 0, 1, 2, -1, NULL, },
  { "DTR", 0, 1, 2, -1, NULL, },
  { "DTR", 0, 1, 2, -1, NULL, },
  { "DTR", 0, 1, 2, -1, NULL, },
  { "DTR", 0, 1, 0, -1, NULL, },
  { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, },
  { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, },
  { "GR0", 14, 1, 0, -1, NULL, },
  { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, },
  { "IBR#", 16, 1, 2, -1, NULL, },
  { "InService*", 17, 1, 7, -1, "SC", },
  { "IP", 0, 1, 0, -1, NULL, },
  { "ITC", 0, 1, 0, -1, NULL, },
  { "ITC", 0, 1, 2, -1, NULL, },
  { "ITC", 0, 1, 2, -1, NULL, },
  { "ITR", 0, 1, 2, -1, NULL, },
  { "ITR", 0, 1, 2, -1, NULL, },
  { "ITR", 0, 1, 0, -1, NULL, },
  { "memory", 0, 1, 0, -1, NULL, },
  { "MSR#", 18, 1, 7, -1, "SC", },
  { "PKR#", 19, 1, 0, -1, NULL, },
  { "PKR#", 19, 1, 0, -1, NULL, },
  { "PKR#", 19, 1, 2, -1, NULL, },
  { "PMC#", 20, 1, 2, -1, NULL, },
  { "PMD#", 21, 1, 2, -1, NULL, },
  { "PR0", 0, 1, 0, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
  { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
  { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, },
  { "PR63", 24, 1, 0, -1, NULL, },
  { "PR63", 24, 1, 0, -1, NULL, },
  { "PR63", 24, 1, 2, -1, NULL, },
  { "PR63", 24, 1, 2, -1, NULL, },
  { "PSR.ac", 28, 1, 2, 3, NULL, },
  { "PSR.be", 28, 1, 2, 1, NULL, },
  { "PSR.bn", 28, 1, 2, 44, NULL, },
  { "PSR.cpl", 28, 1, 2, 32, NULL, },
  { "PSR.da", 28, 1, 2, 38, NULL, },
  { "PSR.db", 28, 1, 2, 24, NULL, },
  { "PSR.dd", 28, 1, 2, 39, NULL, },
  { "PSR.dfh", 28, 1, 2, 19, NULL, },
  { "PSR.dfl", 28, 1, 2, 18, NULL, },
  { "PSR.di", 28, 1, 2, 22, NULL, },
  { "PSR.dt", 28, 1, 2, 17, NULL, },
  { "PSR.ed", 28, 1, 2, 43, NULL, },
  { "PSR.i", 28, 1, 2, 14, NULL, },
  { "PSR.ia", 28, 1, 2, 14, NULL, },
  { "PSR.ic", 28, 1, 2, 13, NULL, },
  { "PSR.id", 28, 1, 2, 14, NULL, },
  { "PSR.is", 28, 1, 2, 14, NULL, },
  { "PSR.it", 28, 1, 2, 14, NULL, },
  { "PSR.lp", 28, 1, 2, 25, NULL, },
  { "PSR.mc", 28, 1, 2, 35, NULL, },
  { "PSR.mfh", 28, 1, 0, 5, NULL, },
  { "PSR.mfh", 28, 1, 2, 5, NULL, },
  { "PSR.mfh", 28, 1, 2, 5, NULL, },
  { "PSR.mfl", 28, 1, 0, 4, NULL, },
  { "PSR.mfl", 28, 1, 2, 4, NULL, },
  { "PSR.mfl", 28, 1, 2, 4, NULL, },
  { "PSR.pk", 28, 1, 2, 15, NULL, },
  { "PSR.pp", 28, 1, 2, 21, NULL, },
  { "PSR.ri", 28, 1, 2, 41, NULL, },
  { "PSR.rt", 28, 1, 2, 27, NULL, },
  { "PSR.si", 28, 1, 2, 23, NULL, },
  { "PSR.sp", 28, 1, 2, 20, NULL, },
  { "PSR.ss", 28, 1, 2, 40, NULL, },
  { "PSR.tb", 28, 1, 2, 26, NULL, },
  { "PSR.up", 28, 1, 2, 2, NULL, },
  { "RR#", 25, 1, 2, -1, NULL, },
  { "RSE", 29, 1, 2, -1, NULL, },
  { "PR63", 24, 2, 6, -1, NULL, },
};

static const short dep0[] = {
  88, 252, 2131, 2297, 
};

static const short dep1[] = {
  32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, 
  20605, 
};

static const short dep2[] = {
  88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2317, 2318, 2321, 
  2322, 2325, 2326, 
};

static const short dep3[] = {
  32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2317, 
  2318, 2321, 2322, 2325, 2326, 4127, 20605, 
};

static const short dep4[] = {
  88, 252, 22637, 22638, 22640, 22641, 22643, 22644, 22646, 22794, 22797, 22798, 
  22801, 22802, 22805, 22806, 
};