m10300-opc.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,153 行 · 第 1/5 页

#define IMM4    (PC+1)
  {4, 0, 0},

/* Processor status word.  */
#define EPSW    (IMM4+1)
  {0, 0, MN10300_OPERAND_EPSW},

/* rn register in the first register operand position.  */
#define RN0      (EPSW+1)
  {4, 0, MN10300_OPERAND_RREG},

/* rn register in the fourth register operand position.  */
#define RN2      (RN0+1)
  {4, 4, MN10300_OPERAND_RREG},

/* rm register in the first register operand position.  */
#define RM0      (RN2+1)
  {4, 0, MN10300_OPERAND_RREG},

/* rm register in the second register operand position.  */
#define RM1      (RM0+1)
  {4, 2, MN10300_OPERAND_RREG},

/* rm register in the third register operand position.  */
#define RM2      (RM1+1)
  {4, 4, MN10300_OPERAND_RREG},

#define RN02      (RM2+1)
  {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},

#define XRN0      (RN02+1)
  {4, 0, MN10300_OPERAND_XRREG},

#define XRM2      (XRN0+1)
  {4, 4, MN10300_OPERAND_XRREG},

/* + for autoincrement */
#define PLUS	(XRM2+1)
  {0, 0, MN10300_OPERAND_PLUS}, 

#define XRN02      (PLUS+1)
  {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},

/* Ick */
#define RD0      (XRN02+1)
  {4, -8, MN10300_OPERAND_RREG},

#define RD2      (RD0+1)
  {4, -4, MN10300_OPERAND_RREG},

/* 8 unsigned displacement in a memory operation which
   may promote to a 32bit displacement.  */
#define IMM8_MEM    (RD2+1)
  {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},

/* Index register.  */
#define RI (IMM8_MEM+1)
  {4, 4, MN10300_OPERAND_RREG},

/* 24 bit signed displacement, may promote to 32bit displacement.  */
#define SD24    (RI+1)
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},

/* 24 bit unsigned immediate which may promote to a 32bit
   unsigned immediate.  */
#define IMM24    (SD24+1)
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},

/* 24 bit signed immediate which may promote to a 32bit
   signed immediate.  */
#define SIMM24    (IMM24+1)
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},

/* 24bit unsigned displacement in a memory operation which
   may promote to a 32bit displacement.  */
#define IMM24_MEM    (SIMM24+1)
  {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
/* 32bit immediate, high 8 bits in the main instruction
   word, 24 in the extension word.

   The "bits" field indicates how many bits are in the
   main instruction word for MN10300_OPERAND_SPLIT!  */
#define IMM32_HIGH8    (IMM24_MEM+1)
  {8, 0, MN10300_OPERAND_SPLIT},

/* Similarly, but a memory address.  */
#define IMM32_HIGH8_MEM  (IMM32_HIGH8+1)
  {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},

/* rm register in the seventh register operand position.  */
#define RM6      (IMM32_HIGH8_MEM+1)
  {4, 12, MN10300_OPERAND_RREG},

/* rm register in the fifth register operand position.  */
#define RN4      (RM6+1)
  {4, 8, MN10300_OPERAND_RREG},

/* 4 bit immediate for dsp instructions.  */
#define IMM4_2    (RN4+1)
  {4, 4, 0},

/* 4 bit immediate for dsp instructions.  */
#define SIMM4_2    (IMM4_2+1)
  {4, 4, MN10300_OPERAND_SIGNED},

/* 4 bit immediate for dsp instructions.  */
#define SIMM4_6    (SIMM4_2+1)
  {4, 12, MN10300_OPERAND_SIGNED},

} ; 

#define MEM(ADDR) PAREN, ADDR, PAREN 
#define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN 
#define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN 
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 

/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK	MATCH_MASK, FORMAT, PROCESSOR	{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov",	0x8000,	     0xf000,	  0,    FMT_S1, 0,	{SIMM8, DN01}},
{ "mov",	0x80,	     0xf0,	  0x3,  FMT_S0, 0,	{DM1, DN0}},
{ "mov",	0xf1e0,	     0xfff0,	  0,    FMT_D0, 0,	{DM1, AN0}},
{ "mov",	0xf1d0,	     0xfff0,	  0,    FMT_D0, 0,	{AM1, DN0}},
{ "mov",	0x9000,	     0xf000,	  0,    FMT_S1, 0,	{IMM8, AN01}},
{ "mov",	0x90,	     0xf0,	  0x3,  FMT_S0, 0,	{AM1, AN0}},
{ "mov",	0x3c,	     0xfc,	  0,    FMT_S0, 0,	{SP, AN0}},
{ "mov",	0xf2f0,	     0xfff3,	  0,    FMT_D0, 0,	{AM1, SP}},
{ "mov",	0xf2e4,	     0xfffc,	  0,    FMT_D0, 0,	{PSW, DN0}},
{ "mov",	0xf2f3,	     0xfff3,	  0,    FMT_D0, 0,	{DM1, PSW}},
{ "mov",	0xf2e0,	     0xfffc,	  0,    FMT_D0, 0,	{MDR, DN0}},
{ "mov",	0xf2f2,	     0xfff3,	  0,    FMT_D0, 0,	{DM1, MDR}},
{ "mov",	0x70,	     0xf0,	  0,    FMT_S0, 0,	{MEM(AM0), DN1}},
{ "mov",	0x5800,	     0xfcff,	  0,    FMT_S1, 0,	{MEM(SP), DN0}},
{ "mov",	0x300000,    0xfc0000,    0,    FMT_S2, 0,	{MEM(IMM16_MEM), DN0}},
{ "mov",	0xf000,	     0xfff0,	  0,    FMT_D0, 0,	{MEM(AM0), AN1}},
{ "mov",	0x5c00,	     0xfcff,	  0,    FMT_S1, 0,	{MEM(SP), AN0}},
{ "mov",	0xfaa00000,  0xfffc0000,  0,    FMT_D2, 0,	{MEM(IMM16_MEM), AN0}},
{ "mov",	0x60,	     0xf0,	  0,    FMT_S0, 0,	{DM1, MEM(AN0)}},
{ "mov",	0x4200,	     0xf3ff,	  0,    FMT_S1, 0,	{DM1, MEM(SP)}},
{ "mov",	0x010000,    0xf30000,    0,    FMT_S2, 0,	{DM1, MEM(IMM16_MEM)}},
{ "mov",	0xf010,	     0xfff0,	  0,    FMT_D0, 0,	{AM1, MEM(AN0)}},
{ "mov",	0x4300,	     0xf3ff,	  0,    FMT_S1, 0,	{AM1, MEM(SP)}},
{ "mov",	0xfa800000,  0xfff30000,  0,    FMT_D2, 0,	{AM1, MEM(IMM16_MEM)}},
{ "mov",	0x5c00,	     0xfc00,	  0,    FMT_S1, 0,	{MEM2(IMM8, SP), AN0}},
{ "mov",	0xf80000,    0xfff000,    0,    FMT_D1, 0,	{MEM2(SD8, AM0), DN1}},
{ "mov",	0xfa000000,  0xfff00000,  0,    FMT_D2, 0,	{MEM2(SD16, AM0), DN1}},
{ "mov",	0x5800,	     0xfc00,	  0,    FMT_S1, 0,	{MEM2(IMM8, SP), DN0}},
{ "mov",	0xfab40000,  0xfffc0000,  0,    FMT_D2, 0,	{MEM2(IMM16, SP), DN0}},
{ "mov",	0xf300,	     0xffc0,	  0,    FMT_D0, 0,	{MEM2(DI, AM0), DN2}},
{ "mov",	0xf82000,    0xfff000,    0,    FMT_D1, 0,	{MEM2(SD8,AM0), AN1}},
{ "mov",	0xfa200000,  0xfff00000,  0,    FMT_D2, 0,	{MEM2(SD16, AM0), AN1}},
{ "mov",	0xfab00000,  0xfffc0000,  0,    FMT_D2, 0,	{MEM2(IMM16, SP), AN0}},
{ "mov",	0xf380,	     0xffc0,	  0,    FMT_D0, 0,	{MEM2(DI, AM0), AN2}},
{ "mov",	0x4300,	     0xf300,	  0,    FMT_S1, 0,	{AM1, MEM2(IMM8, SP)}},
{ "mov",	0xf81000,    0xfff000,    0,    FMT_D1, 0,	{DM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa100000,  0xfff00000,  0,    FMT_D2, 0,	{DM1, MEM2(SD16, AN0)}},
{ "mov",	0x4200,	     0xf300,	  0,    FMT_S1, 0,	{DM1, MEM2(IMM8, SP)}},
{ "mov",	0xfa910000,  0xfff30000,  0,    FMT_D2, 0,	{DM1, MEM2(IMM16, SP)}},
{ "mov",	0xf340,	     0xffc0,	  0,    FMT_D0, 0,	{DM2, MEM2(DI, AN0)}},
{ "mov",	0xf83000,    0xfff000,    0,    FMT_D1, 0,	{AM1, MEM2(SD8, AN0)}},
{ "mov",	0xfa300000,  0xfff00000,  0,    FMT_D2, 0,	{AM1, MEM2(SD16, AN0)}},
{ "mov",	0xfa900000,  0xfff30000,  0,    FMT_D2, 0,	{AM1, MEM2(IMM16, SP)}},
{ "mov",	0xf3c0,	     0xffc0,	  0,    FMT_D0, 0,	{AM2, MEM2(DI, AN0)}},

{ "mov",	0xf020,	     0xfffc,	  0,    FMT_D0, AM33,	{USP, AN0}},
{ "mov",	0xf024,	     0xfffc,	  0,    FMT_D0, AM33,	{SSP, AN0}},
{ "mov",	0xf028,	     0xfffc,	  0,    FMT_D0, AM33,	{MSP, AN0}},
{ "mov",	0xf02c,	     0xfffc,	  0,    FMT_D0, AM33,	{PC, AN0}},
{ "mov",	0xf030,	     0xfff3,	  0,    FMT_D0, AM33,	{AN1, USP}},
{ "mov",	0xf031,	     0xfff3,	  0,    FMT_D0, AM33,	{AN1, SSP}},
{ "mov",	0xf032,	     0xfff3,	  0,    FMT_D0, AM33,	{AN1, MSP}},
{ "mov",	0xf2ec,	     0xfffc,	  0,    FMT_D0, AM33,	{EPSW, DN0}},
{ "mov",	0xf2f1,	     0xfff3,	  0,    FMT_D0, AM33,	{DM1, EPSW}},
{ "mov",	0xf500,	     0xffc0,	  0,    FMT_D0, AM33,	{AM2, RN0}},
{ "mov",	0xf540,	     0xffc0,	  0,    FMT_D0, AM33,	{DM2, RN0}},
{ "mov",	0xf580,	     0xffc0,	  0,    FMT_D0, AM33,	{RM1, AN0}},
{ "mov",	0xf5c0,	     0xffc0,	  0,    FMT_D0, AM33,	{RM1, DN0}},
{ "mov",	0xf90800,    0xffff00,    0,    FMT_D6, AM33,	{RM2, RN0}},
{ "mov",	0xf9e800,    0xffff00,    0,    FMT_D6, AM33,	{XRM2, RN0}},
{ "mov",	0xf9f800,    0xffff00,    0,    FMT_D6, AM33,	{RM2, XRN0}},
{ "mov",	0xf90a00,    0xffff00,    0,    FMT_D6, AM33,	{MEM(RM0), RN2}},
{ "mov",	0xf98a00,    0xffff0f,    0,    FMT_D6, AM33,	{MEM(SP), RN2}},
{ "mov",	0xf96a00,    0xffff00,    0x12, FMT_D6, AM33,	{MEMINC(RM0), RN2}},
{ "mov",	0xfb0e0000,  0xffff0f00,  0,    FMT_D7, AM33,	{MEM(IMM8_MEM), RN2}},
{ "mov",	0xfd0e0000,  0xffff0f00,  0,    FMT_D8, AM33,	{MEM(IMM24_MEM), RN2}},
{ "mov",	0xf91a00,    0xffff00,    0,    FMT_D6, AM33,	{RM2, MEM(RN0)}},
{ "mov",	0xf99a00,    0xffff0f,    0,    FMT_D6, AM33,	{RM2, MEM(SP)}},
{ "mov",	0xf97a00,    0xffff00,    0,	FMT_D6, AM33,	{RM2, MEMINC(RN0)}},
{ "mov",	0xfb1e0000,  0xffff0f00,  0,    FMT_D7, AM33,	{RM2, MEM(IMM8_MEM)}},
{ "mov",	0xfd1e0000,  0xffff0f00,  0,    FMT_D8, AM33,	{RM2, MEM(IMM24_MEM)}},
{ "mov",	0xfb0a0000,  0xffff0000,  0,    FMT_D7, AM33,	{MEM2(SD8, RM0), RN2}},
{ "mov",	0xfd0a0000,  0xffff0000,  0,    FMT_D8, AM33,	{MEM2(SD24, RM0), RN2}},
{ "mov",	0xfb8e0000,  0xffff000f,  0,    FMT_D7, AM33,	{MEM2(RI, RM0), RD2}},
{ "mov",	0xfb1a0000,  0xffff0000,  0,    FMT_D7, AM33,	{RM2, MEM2(SD8, RN0)}},
{ "mov",	0xfd1a0000,  0xffff0000,  0,    FMT_D8, AM33,	{RM2, MEM2(SD24, RN0)}},
{ "mov",	0xfb8a0000,  0xffff0f00,  0,    FMT_D7, AM33,	{MEM2(IMM8, SP), RN2}},
{ "mov",	0xfd8a0000,  0xffff0f00,  0,    FMT_D8, AM33,	{MEM2(IMM24, SP), RN2}},
{ "mov",	0xfb9a0000,  0xffff0f00,  0,    FMT_D7, AM33,	{RM2, MEM2(IMM8, SP)}},
{ "mov",	0xfd9a0000,  0xffff0f00,  0,    FMT_D8, AM33,	{RM2, MEM2(IMM24, SP)}},
{ "mov",	0xfb9e0000,  0xffff000f,  0,    FMT_D7, AM33,	{RD2, MEM2(RI, RN0)}},
{ "mov",	0xfb6a0000,  0xffff0000,  0x22, FMT_D7, AM33,	{MEMINC2 (RM0, SIMM8), RN2}},
{ "mov",	0xfb7a0000,  0xffff0000,  0,	FMT_D7, AM33,	{RM2, MEMINC2 (RN0, SIMM8)}},
{ "mov",	0xfd6a0000,  0xffff0000,  0x22, FMT_D8, AM33,	{MEMINC2 (RM0, IMM24), RN2}},
{ "mov",	0xfd7a0000,  0xffff0000,  0,	FMT_D8, AM33,	{RM2, MEMINC2 (RN0, IMM24)}},
{ "mov",	0xfe6a0000,  0xffff0000,  0x22, FMT_D9, AM33,	{MEMINC2 (RM0, IMM32_HIGH8), RN2}},
{ "mov",	0xfe7a0000,  0xffff0000,  0,	FMT_D9, AM33,	{RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
/* These must come after most of the other move instructions to avoid matching
   a symbolic name with IMMxx operands.  Ugh.  */
{ "mov",	0x2c0000,    0xfc0000,    0,    FMT_S2, 0,	{SIMM16, DN0}},
{ "mov",	0xfccc0000,  0xfffc0000,  0,    FMT_D4, 0,	{IMM32, DN0}},
{ "mov",	0x240000,    0xfc0000,    0,    FMT_S2, 0,	{IMM16, AN0}},
{ "mov",	0xfcdc0000,  0xfffc0000,  0,    FMT_D4, 0,	{IMM32, AN0}},
{ "mov",	0xfca40000,  0xfffc0000,  0,    FMT_D4, 0,	{MEM(IMM32_MEM), DN0}},
{ "mov",	0xfca00000,  0xfffc0000,  0,    FMT_D4, 0,	{MEM(IMM32_MEM), AN0}},
{ "mov",	0xfc810000,  0xfff30000,  0,    FMT_D4, 0,	{DM1, MEM(IMM32_MEM)}},
{ "mov",	0xfc800000,  0xfff30000,  0,    FMT_D4, 0,	{AM1, MEM(IMM32_MEM)}},