m32r-opinst.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 674 行 · 第 1/2 页

  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
  { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_mvtc_ops[] = {
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_nop_ops[] = {
  { END }
};

static const CGEN_OPINST sfmt_rac_ops[] = {
  { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
  { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
  { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
  { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
  { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_rte_ops[] = {
  { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
  { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
  { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
  { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
  { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
  { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
  { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_seth_ops[] = {
  { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_sll3_ops[] = {
  { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_slli_ops[] = {
  { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_st_ops[] = {
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_st_d_ops[] = {
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_stb_ops[] = {
  { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_stb_d_ops[] = {
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
  { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_sth_ops[] = {
  { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_sth_d_ops[] = {
  { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
  { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_st_plus_ops[] = {
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
  { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_trap_ops[] = {
  { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
  { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
  { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
  { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
  { OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
  { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
  { OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
  { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
  { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_unlock_ops[] = {
  { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
  { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
  { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
  { END }
};

static const CGEN_OPINST sfmt_satb_ops[] = {
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_sat_ops[] = {
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
  { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
  { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_sadd_ops[] = {
  { INPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
  { OUTPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
  { END }
};

static const CGEN_OPINST sfmt_macwu1_ops[] = {
  { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
  { END }
};

static const CGEN_OPINST sfmt_mulwu1_ops[] = {
  { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
  { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
  { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
  { END }
};

static const CGEN_OPINST sfmt_sc_ops[] = {
  { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
  { END }
};

#undef INPUT
#undef OUTPUT
#undef END
#undef COND_REF
#undef OP_ENT

/* Operand instance lookup table.  */

static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
  0,
  & sfmt_add_ops[0],
  & sfmt_add3_ops[0],
  & sfmt_add_ops[0],
  & sfmt_and3_ops[0],
  & sfmt_add_ops[0],
  & sfmt_or3_ops[0],
  & sfmt_add_ops[0],
  & sfmt_and3_ops[0],
  & sfmt_addi_ops[0],
  & sfmt_addv_ops[0],
  & sfmt_addv3_ops[0],
  & sfmt_addx_ops[0],
  & sfmt_bc8_ops[0],
  & sfmt_bc24_ops[0],
  & sfmt_beq_ops[0],
  & sfmt_beqz_ops[0],
  & sfmt_beqz_ops[0],
  & sfmt_beqz_ops[0],
  & sfmt_beqz_ops[0],
  & sfmt_beqz_ops[0],
  & sfmt_beqz_ops[0],
  & sfmt_bl8_ops[0],
  & sfmt_bl24_ops[0],
  & sfmt_bcl8_ops[0],
  & sfmt_bcl24_ops[0],
  & sfmt_bc8_ops[0],
  & sfmt_bc24_ops[0],
  & sfmt_beq_ops[0],
  & sfmt_bra8_ops[0],
  & sfmt_bra24_ops[0],
  & sfmt_bcl8_ops[0],
  & sfmt_bcl24_ops[0],
  & sfmt_cmp_ops[0],
  & sfmt_cmpi_ops[0],
  & sfmt_cmp_ops[0],
  & sfmt_cmpi_ops[0],
  & sfmt_cmp_ops[0],
  & sfmt_cmpz_ops[0],
  & sfmt_div_ops[0],
  & sfmt_div_ops[0],
  & sfmt_div_ops[0],
  & sfmt_div_ops[0],
  & sfmt_div_ops[0],
  & sfmt_jc_ops[0],
  & sfmt_jc_ops[0],
  & sfmt_jl_ops[0],
  & sfmt_jmp_ops[0],
  & sfmt_ld_ops[0],
  & sfmt_ld_d_ops[0],
  & sfmt_ld_ops[0],
  & sfmt_ld_d_ops[0],
  & sfmt_ld_ops[0],
  & sfmt_ld_d_ops[0],
  & sfmt_ld_ops[0],
  & sfmt_ld_d_ops[0],
  & sfmt_ld_ops[0],
  & sfmt_ld_d_ops[0],
  & sfmt_ld_plus_ops[0],
  & sfmt_ld24_ops[0],
  & sfmt_ldi8_ops[0],
  & sfmt_ldi16_ops[0],
  & sfmt_lock_ops[0],
  & sfmt_machi_ops[0],
  & sfmt_machi_a_ops[0],
  & sfmt_machi_ops[0],
  & sfmt_machi_a_ops[0],
  & sfmt_machi_ops[0],
  & sfmt_machi_a_ops[0],
  & sfmt_machi_ops[0],
  & sfmt_machi_a_ops[0],
  & sfmt_add_ops[0],
  & sfmt_mulhi_ops[0],
  & sfmt_mulhi_a_ops[0],
  & sfmt_mulhi_ops[0],
  & sfmt_mulhi_a_ops[0],
  & sfmt_mulhi_ops[0],
  & sfmt_mulhi_a_ops[0],
  & sfmt_mulhi_ops[0],
  & sfmt_mulhi_a_ops[0],
  & sfmt_mv_ops[0],
  & sfmt_mvfachi_ops[0],
  & sfmt_mvfachi_a_ops[0],
  & sfmt_mvfachi_ops[0],
  & sfmt_mvfachi_a_ops[0],
  & sfmt_mvfachi_ops[0],
  & sfmt_mvfachi_a_ops[0],
  & sfmt_mvfc_ops[0],
  & sfmt_mvtachi_ops[0],
  & sfmt_mvtachi_a_ops[0],
  & sfmt_mvtachi_ops[0],
  & sfmt_mvtachi_a_ops[0],
  & sfmt_mvtc_ops[0],
  & sfmt_mv_ops[0],
  & sfmt_nop_ops[0],
  & sfmt_mv_ops[0],
  & sfmt_rac_ops[0],
  & sfmt_rac_dsi_ops[0],
  & sfmt_rac_ops[0],
  & sfmt_rac_dsi_ops[0],
  & sfmt_rte_ops[0],
  & sfmt_seth_ops[0],
  & sfmt_add_ops[0],
  & sfmt_sll3_ops[0],
  & sfmt_slli_ops[0],
  & sfmt_add_ops[0],
  & sfmt_sll3_ops[0],
  & sfmt_slli_ops[0],
  & sfmt_add_ops[0],
  & sfmt_sll3_ops[0],
  & sfmt_slli_ops[0],
  & sfmt_st_ops[0],
  & sfmt_st_d_ops[0],
  & sfmt_stb_ops[0],
  & sfmt_stb_d_ops[0],
  & sfmt_sth_ops[0],
  & sfmt_sth_d_ops[0],
  & sfmt_st_plus_ops[0],
  & sfmt_st_plus_ops[0],
  & sfmt_add_ops[0],
  & sfmt_addv_ops[0],
  & sfmt_addx_ops[0],
  & sfmt_trap_ops[0],
  & sfmt_unlock_ops[0],
  & sfmt_satb_ops[0],
  & sfmt_satb_ops[0],
  & sfmt_sat_ops[0],
  & sfmt_cmpz_ops[0],
  & sfmt_sadd_ops[0],
  & sfmt_macwu1_ops[0],
  & sfmt_machi_ops[0],
  & sfmt_mulwu1_ops[0],
  & sfmt_macwu1_ops[0],
  & sfmt_sc_ops[0],
  & sfmt_sc_ops[0],
};

/* Function to call before using the operand instance table.  */

void
m32r_cgen_init_opinst_table (cd)
     CGEN_CPU_DESC cd;
{
  int i;
  const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
  CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
  for (i = 0; i < MAX_INSNS; ++i)
    insns[i].opinst = oi[i];
}