fr30-desc.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,660 行 · 第 1/4 页

    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* i32: 32 bit immediate */
  { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
    { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
/* m4: 4  bit negative immediate */
  { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* i20: 20 bit immediate */
  { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
    { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
/* dir8: 8  bit direct address */
  { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* dir9: 9  bit direct address */
  { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* dir10: 10 bit direct address */
  { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* label9: 9  bit pc relative address */
  { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* label12: 12 bit pc relative address */
  { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* reglist_low_ld: 8 bit low register mask for ldm */
  { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* reglist_hi_ld: 8 bit high register mask for ldm */
  { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* reglist_low_st: 8 bit low register mask for stm */
  { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* reglist_hi_st: 8 bit high register mask for stm */
  { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
    { 0, { (1<<MACH_BASE) } }  },
/* cc: condition codes */
  { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* ccc: coprocessor calc */
  { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* nbit: negative   bit */
  { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* vbit: overflow   bit */
  { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* zbit: zero       bit */
  { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* cbit: carry      bit */
  { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* ibit: interrupt  bit */
  { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* sbit: stack      bit */
  { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* tbit: trace trap bit */
  { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* d0bit: division 0 bit */
  { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* d1bit: division 1 bit */
  { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* ccr: condition code bits */
  { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* scr: system condition bits */
  { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* ilm: interrupt level mask */
  { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
  { 0, 0, 0, 0, 0, {0, {0}} }
};

#undef A

#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))

/* The instruction table.  */

static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
{
  /* Special null first entry.
     A `num' value of zero is thus invalid.
     Also, the special `invalid' insn resides here.  */
  { 0, 0, 0, 0, {0, {0}} },
/* add $Rj,$Ri */
  {
    FR30_INSN_ADD, "add", "add", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* add $u4,$Ri */
  {
    FR30_INSN_ADDI, "addi", "add", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* add2 $m4,$Ri */
  {
    FR30_INSN_ADD2, "add2", "add2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* addc $Rj,$Ri */
  {
    FR30_INSN_ADDC, "addc", "addc", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* addn $Rj,$Ri */
  {
    FR30_INSN_ADDN, "addn", "addn", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* addn $u4,$Ri */
  {
    FR30_INSN_ADDNI, "addni", "addn", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* addn2 $m4,$Ri */
  {
    FR30_INSN_ADDN2, "addn2", "addn2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* sub $Rj,$Ri */
  {
    FR30_INSN_SUB, "sub", "sub", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* subc $Rj,$Ri */
  {
    FR30_INSN_SUBC, "subc", "subc", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* subn $Rj,$Ri */
  {
    FR30_INSN_SUBN, "subn", "subn", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmp $Rj,$Ri */
  {
    FR30_INSN_CMP, "cmp", "cmp", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmp $u4,$Ri */
  {
    FR30_INSN_CMPI, "cmpi", "cmp", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* cmp2 $m4,$Ri */
  {
    FR30_INSN_CMP2, "cmp2", "cmp2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* and $Rj,$Ri */
  {
    FR30_INSN_AND, "and", "and", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* or $Rj,$Ri */
  {
    FR30_INSN_OR, "or", "or", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* eor $Rj,$Ri */
  {
    FR30_INSN_EOR, "eor", "eor", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* and $Rj,@$Ri */
  {
    FR30_INSN_ANDM, "andm", "and", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* andh $Rj,@$Ri */
  {
    FR30_INSN_ANDH, "andh", "andh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* andb $Rj,@$Ri */
  {
    FR30_INSN_ANDB, "andb", "andb", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* or $Rj,@$Ri */
  {
    FR30_INSN_ORM, "orm", "or", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* orh $Rj,@$Ri */
  {
    FR30_INSN_ORH, "orh", "orh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* orb $Rj,@$Ri */
  {
    FR30_INSN_ORB, "orb", "orb", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* eor $Rj,@$Ri */
  {
    FR30_INSN_EORM, "eorm", "eor", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* eorh $Rj,@$Ri */
  {
    FR30_INSN_EORH, "eorh", "eorh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* eorb $Rj,@$Ri */
  {
    FR30_INSN_EORB, "eorb", "eorb", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* bandl $u4,@$Ri */
  {
    FR30_INSN_BANDL, "bandl", "bandl", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* borl $u4,@$Ri */
  {
    FR30_INSN_BORL, "borl", "borl", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* beorl $u4,@$Ri */
  {
    FR30_INSN_BEORL, "beorl", "beorl", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* bandh $u4,@$Ri */
  {
    FR30_INSN_BANDH, "bandh", "bandh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* borh $u4,@$Ri */
  {
    FR30_INSN_BORH, "borh", "borh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* beorh $u4,@$Ri */
  {
    FR30_INSN_BEORH, "beorh", "beorh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* btstl $u4,@$Ri */
  {
    FR30_INSN_BTSTL, "btstl", "btstl", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* btsth $u4,@$Ri */
  {
    FR30_INSN_BTSTH, "btsth", "btsth", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* mul $Rj,$Ri */
  {
    FR30_INSN_MUL, "mul", "mul", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* mulu $Rj,$Ri */
  {
    FR30_INSN_MULU, "mulu", "mulu", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* mulh $Rj,$Ri */
  {
    FR30_INSN_MULH, "mulh", "mulh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* muluh $Rj,$Ri */
  {
    FR30_INSN_MULUH, "muluh", "muluh", 16,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* div0s $Ri */
  {
    FR30_INSN_DIV0S, "div0s", "div0s", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* div0u $Ri */
  {
    FR30_INSN_DIV0U, "div0u", "div0u", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* div1 $Ri */
  {
    FR30_INSN_DIV1, "div1", "div1", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* div2 $Ri */
  {
    FR30_INSN_DIV2, "div2", "div2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* div3 */
  {
    FR30_INSN_DIV3, "div3", "div3", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* div4s */
  {
    FR30_INSN_DIV4S, "div4s", "div4s", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lsl $Rj,$Ri */
  {
    FR30_INSN_LSL, "lsl", "lsl", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lsl $u4,$Ri */
  {
    FR30_INSN_LSLI, "lsli", "lsl", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lsl2 $u4,$Ri */
  {
    FR30_INSN_LSL2, "lsl2", "lsl2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lsr $Rj,$Ri */
  {
    FR30_INSN_LSR, "lsr", "lsr", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lsr $u4,$Ri */
  {
    FR30_INSN_LSRI, "lsri", "lsr", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lsr2 $u4,$Ri */
  {
    FR30_INSN_LSR2, "lsr2", "lsr2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* asr $Rj,$Ri */
  {
    FR30_INSN_ASR, "asr", "asr", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* asr $u4,$Ri */
  {
    FR30_INSN_ASRI, "asri", "asr", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* asr2 $u4,$Ri */
  {
    FR30_INSN_ASR2, "asr2", "asr2", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ldi:8 $i8,$Ri */
  {
    FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ldi:20 $i20,$Ri */
  {
    FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* ldi:32 $i32,$Ri */
  {
    FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
    { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
  },
/* ld @$Rj,$Ri */
  {
    FR30_INSN_LD, "ld", "ld", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lduh @$Rj,$Ri */
  {
    FR30_INSN_LDUH, "lduh", "lduh", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ldub @$Rj,$Ri */
  {
    FR30_INSN_LDUB, "ldub", "ldub", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ld @($R13,$Rj),$Ri */
  {
    FR30_INSN_LDR13, "ldr13", "ld", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lduh @($R13,$Rj),$Ri */
  {
    FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ldub @($R13,$Rj),$Ri */
  {
    FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ld @($R14,$disp10),$Ri */
  {
    FR30_INSN_LDR14, "ldr14", "ld", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* lduh @($R14,$disp9),$Ri */
  {
    FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
    { 0, { (1<<MACH_BASE) } }
  },
/* ldub @($R14,$disp8),$Ri */
  {
    FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
    { 0, { (1<<MACH_BASE) } }
  },