fr30-desc.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,660 行 · 第 1/4 页

/* CPU data for fr30.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#include "sysdep.h"
#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "fr30-desc.h"
#include "fr30-opc.h"
#include "opintl.h"
#include "libiberty.h"

/* Attributes.  */

static const CGEN_ATTR_ENTRY bool_attr[] =
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY MACH_attr[] =
{
  { "base", MACH_BASE },
  { "fr30", MACH_FR30 },
  { "max", MACH_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY ISA_attr[] =
{
  { "fr30", ISA_FR30 },
  { "max", ISA_MAX },
  { 0, 0 }
};

const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

/* Instruction set variants.  */

static const CGEN_ISA fr30_cgen_isa_table[] = {
  { "fr30", 16, 16, 16, 48 },
  { 0, 0, 0, 0, 0 }
};

/* Machine variants.  */

static const CGEN_MACH fr30_cgen_mach_table[] = {
  { "fr30", "fr30", MACH_FR30 },
  { 0, 0, 0 }
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
{
  { "r0", 0, {0, {0}}, 0, 0 },
  { "r1", 1, {0, {0}}, 0, 0 },
  { "r2", 2, {0, {0}}, 0, 0 },
  { "r3", 3, {0, {0}}, 0, 0 },
  { "r4", 4, {0, {0}}, 0, 0 },
  { "r5", 5, {0, {0}}, 0, 0 },
  { "r6", 6, {0, {0}}, 0, 0 },
  { "r7", 7, {0, {0}}, 0, 0 },
  { "r8", 8, {0, {0}}, 0, 0 },
  { "r9", 9, {0, {0}}, 0, 0 },
  { "r10", 10, {0, {0}}, 0, 0 },
  { "r11", 11, {0, {0}}, 0, 0 },
  { "r12", 12, {0, {0}}, 0, 0 },
  { "r13", 13, {0, {0}}, 0, 0 },
  { "r14", 14, {0, {0}}, 0, 0 },
  { "r15", 15, {0, {0}}, 0, 0 },
  { "ac", 13, {0, {0}}, 0, 0 },
  { "fp", 14, {0, {0}}, 0, 0 },
  { "sp", 15, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_gr_names =
{
  & fr30_cgen_opval_gr_names_entries[0],
  19,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
{
  { "cr0", 0, {0, {0}}, 0, 0 },
  { "cr1", 1, {0, {0}}, 0, 0 },
  { "cr2", 2, {0, {0}}, 0, 0 },
  { "cr3", 3, {0, {0}}, 0, 0 },
  { "cr4", 4, {0, {0}}, 0, 0 },
  { "cr5", 5, {0, {0}}, 0, 0 },
  { "cr6", 6, {0, {0}}, 0, 0 },
  { "cr7", 7, {0, {0}}, 0, 0 },
  { "cr8", 8, {0, {0}}, 0, 0 },
  { "cr9", 9, {0, {0}}, 0, 0 },
  { "cr10", 10, {0, {0}}, 0, 0 },
  { "cr11", 11, {0, {0}}, 0, 0 },
  { "cr12", 12, {0, {0}}, 0, 0 },
  { "cr13", 13, {0, {0}}, 0, 0 },
  { "cr14", 14, {0, {0}}, 0, 0 },
  { "cr15", 15, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_cr_names =
{
  & fr30_cgen_opval_cr_names_entries[0],
  16,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
{
  { "tbr", 0, {0, {0}}, 0, 0 },
  { "rp", 1, {0, {0}}, 0, 0 },
  { "ssp", 2, {0, {0}}, 0, 0 },
  { "usp", 3, {0, {0}}, 0, 0 },
  { "mdh", 4, {0, {0}}, 0, 0 },
  { "mdl", 5, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_dr_names =
{
  & fr30_cgen_opval_dr_names_entries[0],
  6,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
{
  { "ps", 0, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_h_ps =
{
  & fr30_cgen_opval_h_ps_entries[0],
  1,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
{
  { "r13", 0, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_h_r13 =
{
  & fr30_cgen_opval_h_r13_entries[0],
  1,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
{
  { "r14", 0, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_h_r14 =
{
  & fr30_cgen_opval_h_r14_entries[0],
  1,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
{
  { "r15", 0, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD fr30_cgen_opval_h_r15 =
{
  & fr30_cgen_opval_h_r15_entries[0],
  1,
  0, 0, 0, 0
};



/* The hardware table.  */

#define A(a) (1 << CONCAT2 (CGEN_HW_,a))

const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
{
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
  { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
  { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
  { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
  { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
  { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
};

#undef A

/* The instruction field table.  */

#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))

const CGEN_IFLD fr30_cgen_ifld_table[] =
{
  { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
  { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { 0, 0, 0, 0, 0, 0, {0, {0}} }
};

#undef A

/* The operand table.  */

#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)

const CGEN_OPERAND fr30_cgen_operand_table[] =
{
/* pc: program counter */
  { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* Ri: destination register */
  { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* Rj: source register */
  { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* Ric: target register coproc insn */
  { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* Rjc: source register coproc insn */
  { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* CRi: coprocessor register */
  { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* CRj: coprocessor register */
  { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* Rs1: dedicated register */
  { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* Rs2: dedicated register */
  { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* R13: General Register 13 */
  { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
    { 0, { (1<<MACH_BASE) } }  },
/* R14: General Register 14 */
  { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
    { 0, { (1<<MACH_BASE) } }  },
/* R15: General Register 15 */
  { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
    { 0, { (1<<MACH_BASE) } }  },
/* ps: Program Status register */
  { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
    { 0, { (1<<MACH_BASE) } }  },
/* u4: 4  bit unsigned immediate */
  { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* u4c: 4  bit unsigned immediate */
  { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* u8: 8  bit unsigned immediate */
  { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* i8: 8  bit unsigned immediate */
  { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* udisp6: 6  bit unsigned immediate */
  { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* disp8: 8  bit signed   immediate */
  { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* disp9: 9  bit signed   immediate */
  { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* disp10: 10 bit signed   immediate */
  { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* s10: 10 bit signed   immediate */
  { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* u10: 10 bit unsigned immediate */
  { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,