alpha-opc.c

基于4个mips核的noc设计

     unsigned insn;
     int *invalid;
{
  if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
    *invalid = 1;
  return 0;
}

/*ARGSUSED*/
static unsigned
insert_zc(insn, value, errmsg)
     unsigned insn;
     int value ATTRIBUTE_UNUSED;
     const char **errmsg ATTRIBUTE_UNUSED;
{
  return insn | 31;
}

static int
extract_zc(insn, invalid)
     unsigned insn;
     int *invalid;
{
  if (invalid != (int *) NULL && (insn & 0x1f) != 31)
    *invalid = 1;
  return 0;
}


/* The displacement field of a Branch format insn.  */

static unsigned
insert_bdisp(insn, value, errmsg)
     unsigned insn;
     int value;
     const char **errmsg;
{
  if (errmsg != (const char **)NULL && (value & 3))
    *errmsg = _("branch operand unaligned");
  return insn | ((value / 4) & 0x1FFFFF);
}

/*ARGSUSED*/
static int
extract_bdisp(insn, invalid)
     unsigned insn;
     int *invalid ATTRIBUTE_UNUSED;
{
  return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
}


/* The hint field of a JMP/JSR insn.  */

static unsigned
insert_jhint(insn, value, errmsg)
     unsigned insn;
     int value;
     const char **errmsg;
{
  if (errmsg != (const char **)NULL && (value & 3))
    *errmsg = _("jump hint unaligned");
  return insn | ((value / 4) & 0x3FFF);
}

/*ARGSUSED*/
static int
extract_jhint(insn, invalid)
     unsigned insn;
     int *invalid ATTRIBUTE_UNUSED;
{
  return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
}

/* The hint field of an EV6 HW_JMP/JSR insn.  */

static unsigned
insert_ev6hwjhint(insn, value, errmsg)
     unsigned insn;
     int value;
     const char **errmsg;
{
  if (errmsg != (const char **)NULL && (value & 3))
    *errmsg = _("jump hint unaligned");
  return insn | ((value / 4) & 0x1FFF);
}

/*ARGSUSED*/
static int
extract_ev6hwjhint(insn, invalid)
     unsigned insn;
     int *invalid ATTRIBUTE_UNUSED;
{
  return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
}


/* Macros used to form opcodes */

/* The main opcode */
#define OP(x)		(((x) & 0x3F) << 26)
#define OP_MASK		0xFC000000

/* Branch format instructions */
#define BRA_(oo)	OP(oo)
#define BRA_MASK	OP_MASK
#define BRA(oo)		BRA_(oo), BRA_MASK

/* Floating point format instructions */
#define FP_(oo,fff)	(OP(oo) | (((fff) & 0x7FF) << 5))
#define FP_MASK		(OP_MASK | 0xFFE0)
#define FP(oo,fff)	FP_(oo,fff), FP_MASK

/* Memory format instructions */
#define MEM_(oo)	OP(oo)
#define MEM_MASK	OP_MASK
#define MEM(oo)		MEM_(oo), MEM_MASK

/* Memory/Func Code format instructions */
#define MFC_(oo,ffff)	(OP(oo) | ((ffff) & 0xFFFF))
#define MFC_MASK	(OP_MASK | 0xFFFF)
#define MFC(oo,ffff)	MFC_(oo,ffff), MFC_MASK

/* Memory/Branch format instructions */
#define MBR_(oo,h)	(OP(oo) | (((h) & 3) << 14))
#define MBR_MASK	(OP_MASK | 0xC000)
#define MBR(oo,h)	MBR_(oo,h), MBR_MASK

/* Operate format instructions.  The OPRL variant specifies a
   literal second argument. */
#define OPR_(oo,ff)	(OP(oo) | (((ff) & 0x7F) << 5))
#define OPRL_(oo,ff)	(OPR_((oo),(ff)) | 0x1000)
#define OPR_MASK	(OP_MASK | 0x1FE0)
#define OPR(oo,ff)	OPR_(oo,ff), OPR_MASK
#define OPRL(oo,ff)	OPRL_(oo,ff), OPR_MASK

/* Generic PALcode format instructions */
#define PCD_(oo)	OP(oo)
#define PCD_MASK	OP_MASK
#define PCD(oo)		PCD_(oo), PCD_MASK

/* Specific PALcode instructions */
#define SPCD_(oo,ffff)	(OP(oo) | ((ffff) & 0x3FFFFFF))
#define SPCD_MASK	0xFFFFFFFF
#define SPCD(oo,ffff)	SPCD_(oo,ffff), SPCD_MASK

/* Hardware memory (hw_{ld,st}) instructions */
#define EV4HWMEM_(oo,f)	(OP(oo) | (((f) & 0xF) << 12))
#define EV4HWMEM_MASK	(OP_MASK | 0xF000)
#define EV4HWMEM(oo,f)	EV4HWMEM_(oo,f), EV4HWMEM_MASK

#define EV5HWMEM_(oo,f)	(OP(oo) | (((f) & 0x3F) << 10))
#define EV5HWMEM_MASK	(OP_MASK | 0xF800)
#define EV5HWMEM(oo,f)	EV5HWMEM_(oo,f), EV5HWMEM_MASK

#define EV6HWMEM_(oo,f)	(OP(oo) | (((f) & 0xF) << 12))
#define EV6HWMEM_MASK	(OP_MASK | 0xF000)
#define EV6HWMEM(oo,f)	EV6HWMEM_(oo,f), EV6HWMEM_MASK

#define EV6HWMBR_(oo,h)	(OP(oo) | (((h) & 7) << 13))
#define EV6HWMBR_MASK	(OP_MASK | 0xE000)
#define EV6HWMBR(oo,h)	EV6HWMBR_(oo,h), EV6HWMBR_MASK

/* Abbreviations for instruction subsets.  */
#define BASE			AXP_OPCODE_BASE
#define EV4			AXP_OPCODE_EV4
#define EV5			AXP_OPCODE_EV5
#define EV6			AXP_OPCODE_EV6
#define BWX			AXP_OPCODE_BWX
#define CIX			AXP_OPCODE_CIX
#define MAX			AXP_OPCODE_MAX

/* Common combinations of arguments */
#define ARG_NONE		{ 0 }
#define ARG_BRA			{ RA, BDISP }
#define ARG_FBRA		{ FA, BDISP }
#define ARG_FP			{ FA, FB, DFC1 }
#define ARG_FPZ1		{ ZA, FB, DFC1 }
#define ARG_MEM			{ RA, MDISP, PRB }
#define ARG_FMEM		{ FA, MDISP, PRB }
#define ARG_OPR			{ RA, RB, DRC1 }
#define ARG_OPRL		{ RA, LIT, DRC1 }
#define ARG_OPRZ1		{ ZA, RB, DRC1 }
#define ARG_OPRLZ1		{ ZA, LIT, RC }
#define ARG_PCD			{ PALFN }
#define ARG_EV4HWMEM		{ RA, EV4HWDISP, PRB }
#define ARG_EV4HWMPR		{ RA, RBA, EV4HWINDEX }
#define ARG_EV5HWMEM		{ RA, EV5HWDISP, PRB }
#define ARG_EV6HWMEM		{ RA, EV6HWDISP, PRB }

/* The opcode table.

   The format of the opcode table is:

   NAME OPCODE MASK { OPERANDS }

   NAME		is the name of the instruction.

   OPCODE	is the instruction opcode.

   MASK		is the opcode mask; this is used to tell the disassembler
            	which bits in the actual opcode must match OPCODE.

   OPERANDS	is the list of operands.

   The preceding macros merge the text of the OPCODE and MASK fields.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.

   Otherwise, it is sorted by major opcode and minor function code.

   There are three classes of not-really-instructions in this table:

   ALIAS	is another name for another instruction.  Some of
		these come from the Architecture Handbook, some
		come from the original gas opcode tables.  In all
		cases, the functionality of the opcode is unchanged.

   PSEUDO	a stylized code form endorsed by Chapter A.4 of the
		Architecture Handbook.

   EXTRA	a stylized code form found in the original gas tables.

   And two annotations:

   EV56 BUT	opcodes that are officially introduced as of the ev56,
   		but with defined results on previous implementations.

   EV56 UNA	opcodes that were introduced as of the ev56 with
   		presumably undefined results on previous implementations
		that were not assigned to a particular extension.
*/

const struct alpha_opcode alpha_opcodes[] = {
  { "halt",		SPCD(0x00,0x0000), BASE, ARG_NONE },
  { "draina",		SPCD(0x00,0x0002), BASE, ARG_NONE },
  { "bpt",		SPCD(0x00,0x0080), BASE, ARG_NONE },
  { "callsys",		SPCD(0x00,0x0083), BASE, ARG_NONE },
  { "chmk", 		SPCD(0x00,0x0083), BASE, ARG_NONE },
  { "imb",		SPCD(0x00,0x0086), BASE, ARG_NONE },
  { "call_pal",		PCD(0x00), BASE, ARG_PCD },
  { "pal",		PCD(0x00), BASE, ARG_PCD },		/* alias */

  { "lda",		MEM(0x08), BASE, ARG_MEM },
  { "ldah",		MEM(0x09), BASE, ARG_MEM },
  { "ldbu",		MEM(0x0A), BWX, ARG_MEM },
  { "unop",		MEM(0x0B), BASE, { ZA } },		/* pseudo */
  { "ldq_u",		MEM(0x0B), BASE, ARG_MEM },
  { "ldwu",		MEM(0x0C), BWX, ARG_MEM },
  { "stw",		MEM(0x0D), BWX, ARG_MEM },
  { "stb",		MEM(0x0E), BWX, ARG_MEM },
  { "stq_u",		MEM(0x0F), BASE, ARG_MEM },

  { "sextl",		OPR(0x10,0x00), BASE, ARG_OPRZ1 },	/* pseudo */
  { "sextl",		OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },	/* pseudo */
  { "addl",		OPR(0x10,0x00), BASE, ARG_OPR },
  { "addl",		OPRL(0x10,0x00), BASE, ARG_OPRL },
  { "s4addl",		OPR(0x10,0x02), BASE, ARG_OPR },
  { "s4addl",		OPRL(0x10,0x02), BASE, ARG_OPRL },
  { "negl",		OPR(0x10,0x09), BASE, ARG_OPRZ1 },	/* pseudo */
  { "negl",		OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },	/* pseudo */
  { "subl",		OPR(0x10,0x09), BASE, ARG_OPR },
  { "subl",		OPRL(0x10,0x09), BASE, ARG_OPRL },
  { "s4subl",		OPR(0x10,0x0B), BASE, ARG_OPR },
  { "s4subl",		OPRL(0x10,0x0B), BASE, ARG_OPRL },
  { "cmpbge",		OPR(0x10,0x0F), BASE, ARG_OPR },
  { "cmpbge",		OPRL(0x10,0x0F), BASE, ARG_OPRL },
  { "s8addl",		OPR(0x10,0x12), BASE, ARG_OPR },
  { "s8addl",		OPRL(0x10,0x12), BASE, ARG_OPRL },
  { "s8subl",		OPR(0x10,0x1B), BASE, ARG_OPR },
  { "s8subl",		OPRL(0x10,0x1B), BASE, ARG_OPRL },
  { "cmpult",		OPR(0x10,0x1D), BASE, ARG_OPR },
  { "cmpult",		OPRL(0x10,0x1D), BASE, ARG_OPRL },
  { "addq",		OPR(0x10,0x20), BASE, ARG_OPR },
  { "addq",		OPRL(0x10,0x20), BASE, ARG_OPRL },
  { "s4addq",		OPR(0x10,0x22), BASE, ARG_OPR },
  { "s4addq",		OPRL(0x10,0x22), BASE, ARG_OPRL },
  { "negq", 		OPR(0x10,0x29), BASE, ARG_OPRZ1 },	/* pseudo */
  { "negq", 		OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },	/* pseudo */
  { "subq",		OPR(0x10,0x29), BASE, ARG_OPR },
  { "subq",		OPRL(0x10,0x29), BASE, ARG_OPRL },
  { "s4subq",		OPR(0x10,0x2B), BASE, ARG_OPR },
  { "s4subq",		OPRL(0x10,0x2B), BASE, ARG_OPRL },
  { "cmpeq",		OPR(0x10,0x2D), BASE, ARG_OPR },
  { "cmpeq",		OPRL(0x10,0x2D), BASE, ARG_OPRL },
  { "s8addq",		OPR(0x10,0x32), BASE, ARG_OPR },
  { "s8addq",		OPRL(0x10,0x32), BASE, ARG_OPRL },
  { "s8subq",		OPR(0x10,0x3B), BASE, ARG_OPR },
  { "s8subq",		OPRL(0x10,0x3B), BASE, ARG_OPRL },
  { "cmpule",		OPR(0x10,0x3D), BASE, ARG_OPR },
  { "cmpule",		OPRL(0x10,0x3D), BASE, ARG_OPRL },
  { "addl/v",		OPR(0x10,0x40), BASE, ARG_OPR },
  { "addl/v",		OPRL(0x10,0x40), BASE, ARG_OPRL },
  { "negl/v",		OPR(0x10,0x49), BASE, ARG_OPRZ1 },	/* pseudo */