changelog-9297

来自「基于4个mips核的noc设计」· 代码 · 共 1,888 行 · 第 1/5 页

	* d10v-opc.c (pre_defined_registers):  Add cr[0-15], dpc, dpsw, link.

Mon Dec 16 13:00:15 1996  Jeffrey A Law  ([e-mail])

	* mn10200-opc.c (mn10200_operands): Add SIMM16N.
	(mn10200_opcodes): Use it for some logicals and btst insns.
	Add "break" and "trap" instructions.

	* mn10300-opc.c (mn10300_opcodes): Add "break" instruction.

	* mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".

Sat Dec 14 22:36:20 1996  Ian Lance Taylor  <[e-mail]>

	* mips-dis.c (print_mips16_insn_arg): The base address of a PC
	relative load or add now depends upon whether the instruction is
	in a delay slot.

Wed Dec 11 09:23:46 1996  Jeffrey A Law  ([e-mail])

	* mn10200-dis.c: Finish writing disassembler.
	* mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
	Fix mask for "jmp (an)".

	* mn10300-dis.c (disassemble, print_insn_mn10300): Corrently
	handle endianness issues for mn10300.

	* mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".

Tue Dec 10 12:08:05 1996  Jeffrey A Law  ([e-mail])

	* mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
	instruction.  Fix opcode field for "movb (imm24),dn".

	* mn10200-opc.c (mn10200_operands): Fix insertion position
	for DI operand.

Mon Dec  9 16:42:43 1996  Jeffrey A Law  ([e-mail])

	* mn10200-opc.c: Create mn10200 opcode table.
	* mn10200-dis.c: Flesh out mn10200 disassembler.  Not ready,
	but moving along nicely.

Sun Dec  8 04:28:31 1996  Peter Schauer  ([e-mail])

	* Makefile.in (ALL_MACHINES):  Add mips16-opc.o.

Fri Dec  6 16:47:40 1996  J.T. Conklin  <[e-mail]>

	* m68k-opc.c (m68k_opcodes): Revert change to use < and >
	specifiers for fmovem* instructions.

Fri Dec  6 14:48:09 1996  Jeffrey A Law  ([e-mail])

	* mn10300-dis.c (disassemble): Remove '$' register prefixing.

Fri Dec  6 17:34:39 1996  Ian Lance Taylor  <[e-mail]>

	* mips16-opc.c: Change opcode for entry/exit to avoid conflicting
	with dsrl.

Fri Dec  6 14:48:09 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c: Add some comments explaining the various
	operands and such.

	* mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.

Thu Dec  5 12:09:48 1996  J.T. Conklin  <[e-mail]>

	* m68k-dis.c (print_insn_arg): Handle new < and > operand
	specifiers.

	* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
	operand specifiers in fmovm* instructions.

Wed Dec  4 14:52:18 1996  Ian Lance Taylor  <[e-mail]>

	* ppc-opc.c (insert_li): Give an error if the offset has the two
	least significant bits set.

Wed Nov 27 13:09:01 1996  Ian Lance Taylor  <[e-mail]>

	* mips-dis.c (print_insn_mips16): Separate the instruction from
	the arguments with a tab, not a space.

Tue Nov 26 13:24:17 1996  Jeffrey A Law  ([e-mail])

	* mn10300-dis.c (disasemble): Finish conversion to '$' as
	register prefix.

	* mn10300-opc.c (mn10300_opcodes): Fix mask field for
	mov am,(imm32,sp).

Tue Nov 26 10:53:21 1996  Ian Lance Taylor  <[e-mail]>

	* configure: Rebuild with autoconf 2.12.

	Add support for mips16 (16 bit MIPS implementation):
	* mips16-opc.c: New file.
	* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
	(mips16_reg_names): New static array.
	(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
	after seeing a 16 bit symbol.
	(print_insn_little_mips): Likewise.
	(print_insn_mips16): New static function.
	(print_mips16_insn_arg): New static function.
	* mips-opc.c: Add jalx instruction.
	* Makefile.in (mips16-opc.o): New target.
	* configure.in: Use mips16-opc.o for bfd_mips_arch.
	* configure: Rebuild.

Mon Nov 25 16:15:17 1996  J.T. Conklin  <[e-mail]>

	* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
	operand specifiers in *save, *restore and movem* instructions.

	* m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
	the coldfire.

	* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
	register operands for immediate arithmetic, not, neg, negx, and
	set according to condition instructions.

	* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
	specifier of the effective-address operand in immediate forms of
	arithmetic instructions.  The specifier for the immediate operand
	notes how and where the constant will be stored.

Mon Nov 25 11:17:01 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
	opcode.

	* mn10300-dis.c (disassemble): Use '$' instead of '%' for
	register prefix.

	* mn10300-dis.c (disassemble): Prefix registers with '%'.

Wed Nov 20 10:37:13 1996  Jeffrey A Law  ([e-mail])

	* mn10300-dis.c (disassemble): Handle register lists.

	* mn10300-opc.c: Fix handling of register list operand for
	"call", "ret", and "rets" instructions.

	* mn10300-dis.c (disassemble): Print PC-relative and memory
	addresses symbolically if possible.
	* mn10300-opc.c: Distinguish between absolute memory addresses,
	pc-relative offsets & random immediates.

	* mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte
	in 7 byte insns.
	(disassemble): Handle SPLIT and EXTENDED operands.

Tue Nov 19 13:33:01 1996  Jeffrey A Law  ([e-mail])

	* mn10300-dis.c: Rough cut at printing some operands.

	* mn10300-dis.c: Start working on disassembler support.
	* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.

	* mn10300-opc.c (mn10300_operands): Add "REGS" for a register
	list.
	(mn10300_opcodes): Use REGS for register list in "movm" instructions.

Mon Nov 18 15:20:35 1996  Michael Meissner  <[e-mail]>

	* d10v-opc.c (d10v_opcodes): Add3 sets the carry.

Fri Nov 15 13:43:19 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_opcodes): Demand parens around
	register argument is calls and jmp instructions.

Thu Nov  7 00:26:05 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and
	getx operand.  Fix opcode for mulqu imm,dn.

Wed Nov  6 13:42:32 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_operands): Hijack "bits" field
	in MN10300_OPERAND_SPLIT operands for how many bits
	appear in the basic insn word.  Add IMM32_HIGH24,
	IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
	(mn10300_opcodes): Use new operands as needed.

	* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
	for bset, bclr, btst instructions.
	(mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.

	* mn10300-opc.c (mn10300_operands): Remove many redundant
	operands.  Update opcode table as appropriate.
	(IMM32): Add MN10300_OPERAND_SPLIT flag.
	(mn10300_opcodes): Fix single bit error in mov imm32,dn insn.

Tue Nov  5 13:26:58 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
	operands (for indexed load/stores).  Fix bitpos for DI
	operand.  Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
	few instructions that insert immediates/displacements in the
	middle of the instruction.  Add IMM8E for 8 bit immediate in
	the extended part of an instruction.
	(mn10300_operands): Use new opcodes as appropriate.

Tue Nov  5 10:30:51 1996  Martin M. Hunt  <[e-mail]>

	* d10v-opc.c (d10v_opcodes): Declare the trap instruction
	sequential so the assembler never parallelizes it with
	other instructions.

Mon Nov  4 12:50:40 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
	a data/address register that appears in register field 0
	and register field 1.
	(mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN

Fri Nov  1 10:29:11 1996  Richard Henderson  <[e-mail]>

	* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
	standard disassembly.

	* alpha-opc.c (alpha_operands): Rearrange flags slot.
	(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
	Recategorize PALcode instructions.

Wed Oct 30 16:46:58 1996  Jeffrey A Law  ([e-mail])

	* v850-opc.c (v850_opcodes): Add relaxing "jbr".

Tue Oct 29 16:30:28 1996  Ian Lance Taylor  <[e-mail]>

	* mips-dis.c (_print_insn_mips): Don't print a trailing tab if
	there are no operand types.

Tue Oct 29 12:22:21 1996  Jeffrey A Law  ([e-mail])

	* v850-opc.c (D9_RELAX): Renamed from D9, all references
	changed.
	(v850_operands): Make sure D22 immediately follows D9_RELAX.

Fri Oct 25 12:12:53 1996  Ian Lance Taylor  <[e-mail]>

	* i386-dis.c (print_insn_x86): Set info->bytes_per_line to 5.

Thu Oct 24 17:53:52 1996  Jeffrey A Law  ([e-mail])

	* v850-opc.c (insert_d8_6): Fix operand insertion for sld.w
	and sst.w instructions.

	* v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
	"bCC"instructions).

Thu Oct 24 17:21:20 1996  Ian Lance Taylor  <[e-mail]>

	* mips-dis.c (_print_insn_mips): Use a tab between the instruction
	and the arguments.

Tue Oct 22 23:32:56 1996  Ian Lance Taylor  <[e-mail]>

	* ppc-opc.c (PPCPWR2): Define.
	(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
	it.

Fri Oct 11 16:03:49 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
	field for movhu instruction.

	* v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
	cast value to "long" not "signed long" to keep hpux10
	compiler quiet.

Thu Oct 10 10:25:58 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
	for mov (abs16),DN.

	* mn10300-opc.c (FMT*): Remove definitions.

	* mn10300-opc.c (mn10300_opcodes): Fix destination register
	for shift-by-register opcodes.

	* mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
	into [AD][MN][01] for encoding the position of the register
	in the opcode.

Wed Oct  9 11:19:26 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
	"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".

Tue Oct  8 11:55:35 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
	Fix various typos.  Add "PAREN" operand.
	(MEM, MEM2): Define.
	(mn10300_opcodes): Surround all memory addresses with "PAREN"
	operands.  Fix several typos.

	* mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
	changes.

Mon Oct  7 16:48:45 1996  Jeffrey A Law  ([e-mail])

	* mn10300-opc.c (FMT_XX): Renumber starting at one.
	(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
	at this time.
	(mn10300_opcodes): Break opcode format out into its own field.
	Update many operand fields to deal with signed vs unsigned
	issues.  Fix one or two typos in the "mov" instruction
	opcode, mask and/or operand fields.

Mon Oct  7 11:39:49 1996  Andreas Schwab  <[e-mail]>

	* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
	m68851 wasn't reset.

Thu Oct  3 17:17:02 1996  Ian Lance Taylor  <[e-mail]>

	* mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
	all opcodes.  Very rough cut at operands for all opcodes.

	* mn10300-opc.c (mn10300_opcodes): Start fleshing out the
	opcode table.

Thu Oct  3 10:06:07 1996  Jeffrey A Law  ([e-mail])

	* mn10200-opc.c, mn10300-opc.c: New files.
	* mn10200-dis.c, mn10300-dis.c: New files.
	* mn10x00-opc.c, mn10x00-dis.c: Deleted.
	* disassemble.c: Break mn10x00 support into 10200 and 10300
	support.
	* configure.in: Likewise.
	* configure: Rebuilt.

Thu Oct  3 15:59:12 1996  Jason Molenda  ([e-mail])

	* Makefile.in (MOSTLYCLEAN): Move config.log to distclean.

Wed Oct  2 23:28:42 1996  Jeffrey A Law  ([e-mail])

	* mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita
	MN10x00 processors.
	* disassemble (ARCH_mn10x00): Define.
	(disassembler): Handle bfd_arch_mn10x00.
	* configure.in: Recognize bfd_mn10x00_arch.
	* configure: Rebuilt.

Tue Oct  1 10:49:11 1996  Ian Lance Taylor  <[e-mail]>

	* i386-dis.c (op_rtn): Change to be a pointer.  Adjust uses
	accordingly.  Don't declare functions using op_rtn.

Fri Sep 27 18:28:59 1996  Stu Grossman  ([e-mail])

	* v850-dis.c (disassemble):  Add memaddr argument.  Re-arrange
	params to be more standard.
	* (disassemble):  Print absolute addresses and symbolic names for
	branch and jump targets.
	* v850-opc.c (v850_operand):  Add displacement flag to 9 and 22
	bit operands.
	* (v850_opcodes):  Add breakpoint insn.

Mon Sep 23 12:32:26 1996  Ian Lance Taylor  <[e-mail]>

	* m68k-opc.c: Move the fmovemx data register cases before the
	other cases, so that they get recognized before the data register
	does gets treated as a degenerate register list.

Tue Sep 17 12:06:51 1996  Ian Lance Taylor  <[e-mail]>

	* mips-opc.c: Add a case for "div" and "divu" with two registers
	and a destination of $0.