tic54x-opc.c

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/* Table of opcodes for the Texas Instruments TMS320C54X
   Copyright 1999, 2000 Free Software Foundation, Inc.
   Contributed by Timothy Wall ([e-mail])

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

#include "sysdep.h"
#include "opcode/tic54x.h"

/* these are the only register names not found in mmregs */
const symbol regs[] = {
  { "AR0", 16 },                  { "ar0", 16 },                               
  { "AR1", 17 },                  { "ar1", 17 },                               
  { "AR2", 18 },                  { "ar2", 18 },                               
  { "AR3", 19 },                  { "ar3", 19 },                               
  { "AR4", 20 },                  { "ar4", 20 },                               
  { "AR5", 21 },                  { "ar5", 21 },                               
  { "AR6", 22 },                  { "ar6", 22 },                               
  { "AR7", 23 },                  { "ar7", 23 },                               
  { NULL, }
};

/* status bits, MM registers, condition codes, etc */
/* some symbols are only valid for certain chips... */
const symbol mmregs[] = {
  { "IMR", 0 },                   { "imr", 0 },                                
  { "IFR", 1 },                   { "ifr", 1 },                                
  { "ST0", 6 },                   { "st0", 6 },                                
  { "ST1", 7 },                   { "st1", 7 },                                
  { "AL",  8 },                   { "al",  8 },                                
  { "AH",  9 },                   { "ah",  9 },                                
  { "AG",  10 },                  { "ag",  10 },                               
  { "BL",  11 },                  { "bl",  11 },                               
  { "BH",  12 },                  { "bh",  12 },                               
  { "BG",  13 },                  { "bg",  13 },                               
  { "T",   14 },                  { "t",   14 },                               
  { "TRN", 15 },                  { "trn", 15 },                               
  { "AR0", 16 },                  { "ar0", 16 },                               
  { "AR1", 17 },                  { "ar1", 17 },                               
  { "AR2", 18 },                  { "ar2", 18 },                               
  { "AR3", 19 },                  { "ar3", 19 },                               
  { "AR4", 20 },                  { "ar4", 20 },                               
  { "AR5", 21 },                  { "ar5", 21 },                               
  { "AR6", 22 },                  { "ar6", 22 },                               
  { "AR7", 23 },                  { "ar7", 23 },                               
  { "SP",  24 },                  { "sp",  24 },                               
  { "BK",  25 },                  { "bk",  25 },                               
  { "BRC", 26 },                  { "brc", 26 },                               
  { "RSA", 27 },                  { "rsa", 27 },                               
  { "REA", 28 },                  { "rea", 28 },                               
  { "PMST",29 },                  { "pmst",29 },                               
  { "XPC", 30 },                  { "xpc", 30 }, /* 'c548 only */              
  /* optional peripherals */      /* optional peripherals */                   
  { "M1F", 31 },                  { "m1f", 31 },                               
  { "DRR0",0x20 },                { "drr0",0x20 },                             
  { "BDRR0",0x20 },               { "bdrr0",0x20 }, /* 'c543, 545 */           
  { "DXR0",0x21 },                { "dxr0",0x21 },                             
  { "BDXR0",0x21 },               { "bdxr0",0x21 }, /* 'c543, 545 */           
  { "SPC0",0x22 },                { "spc0",0x22 },                             
  { "BSPC0",0x22 },               { "bspc0",0x22 }, /* 'c543, 545 */           
  { "SPCE0",0x23 },               { "spce0",0x23 },                            
  { "BSPCE0",0x23 },              { "bspce0",0x23 }, /* 'c543, 545 */          
  { "TIM", 0x24 },                { "tim", 0x24 },                             
  { "PRD", 0x25 },                { "prd", 0x25 },                             
  { "TCR", 0x26 },                { "tcr", 0x26 },                             
  { "SWWSR",0x28 },               { "swwsr",0x28 },                            
  { "BSCR",0x29 },                { "bscr",0x29 },                             
  { "HPIC",0x2C },                { "hpic",0x2c },                             
  /* 'c541, 'c545 */              /* 'c541, 'c545 */                           
  { "DRR1",0x30 },                { "drr1",0x30 },                             
  { "DXR1",0x31 },                { "dxr1",0x31 },                             
  { "SPC1",0x32 },                { "spc1",0x32 },                             
  /* 'c542, 'c543 */              /* 'c542, 'c543 */                           
  { "TRCV",0x30 },                { "trcv",0x30 },                             
  { "TDXR",0x31 },                { "tdxr",0x31 },                             
  { "TSPC",0x32 },                { "tspc",0x32 },                             
  { "TCSR",0x33 },                { "tcsr",0x33 },                             
  { "TRTA",0x34 },                { "trta",0x34 },                             
  { "TRAD",0x35 },                { "trad",0x35 },                             
  { "AXR0",0x38 },                { "axr0",0x38 },                             
  { "BKX0",0x39 },                { "bkx0",0x39 },                             
  { "ARR0",0x3A },                { "arr0",0x3a },                             
  { "BKR0",0x3B },                { "bkr0",0x3b },                             
  /* 'c545, 'c546, 'c548 */       /* 'c545, 'c546, 'c548 */                    
  { "CLKMD",0x58 },               { "clkmd",0x58 },                            
  /* 'c548 */                     /* 'c548 */                                  
  { "AXR1",0x3C },                { "axr1",0x3c },                             
  { "BKX1",0x3D },                { "bkx1",0x3d },                             
  { "ARR1",0x3E },                { "arr1",0x3e },                             
  { "BKR1",0x3F },                { "bkr1",0x3f },                             
  { "BDRR1",0x40 },               { "bdrr1",0x40 },                            
  { "BDXR1",0x41 },               { "bdxr1",0x41 },                            
  { "BSPC1",0x42 },               { "bspc1",0x42 },                            
  { "BSPCE1",0x43 },              { "bspce1",0x43 },                           
  { NULL },
};

const symbol condition_codes[] = {
  /* condition codes */
  { "UNC",  0 },                { "unc",  0 },
#define CC1   0x40
#define CCB   0x08
#define CCEQ  0x05
#define CCNEQ 0x04
#define CCLT  0x03
#define CCLEQ 0x07
#define CCGT  0x06
#define CCGEQ 0x02
#define CCOV  0x70
#define CCNOV 0x60
#define CCBIO 0x03
#define CCNBIO 0x02
#define CCTC  0x30
#define CCNTC 0x20
#define CCC   0x0C
#define CCNC  0x08
  { "aeq",  CC1|CCEQ },         { "AEQ",  CC1|CCEQ },
  { "aneq", CC1|CCNEQ },        { "ANEQ", CC1|CCNEQ },
  { "alt",  CC1|CCLT },         { "ALT",  CC1|CCLT },
  { "aleq", CC1|CCLEQ },        { "ALEQ", CC1|CCLEQ },
  { "agt",  CC1|CCGT },         { "AGT",  CC1|CCGT },  
  { "ageq", CC1|CCGEQ },        { "AGEQ", CC1|CCGEQ },  
  { "aov",  CC1|CCOV },         { "AOV",  CC1|CCOV },  
  { "anov", CC1|CCNOV },        { "ANOV", CC1|CCNOV },  
  { "beq",  CC1|CCB|CCEQ },     { "BEQ",  CC1|CCB|CCEQ },  
  { "bneq", CC1|CCB|CCNEQ },    { "BNEQ", CC1|CCB|CCNEQ },  
  { "blt",  CC1|CCB|CCLT },     { "BLT",  CC1|CCB|CCLT },  
  { "bleq", CC1|CCB|CCLEQ },    { "BLEQ", CC1|CCB|CCLEQ },  
  { "bgt",  CC1|CCB|CCGT },     { "BGT",  CC1|CCB|CCGT },  
  { "bgeq", CC1|CCB|CCGEQ },    { "BGEQ", CC1|CCB|CCGEQ },  
  { "bov",  CC1|CCB|CCOV },     { "BOV",  CC1|CCB|CCOV },  
  { "bnov", CC1|CCB|CCNOV },    { "BNOV", CC1|CCB|CCNOV },  
  { "tc",   CCTC },             { "TC",   CCTC },  
  { "ntc",  CCNTC },            { "NTC",  CCNTC },  
  { "c",    CCC },              { "C",    CCC },  
  { "nc",   CCNC },             { "NC",   CCNC },  
  { "bio",  CCBIO },            { "BIO",  CCBIO },  
  { "nbio", CCNBIO },           { "NBIO", CCNBIO },  
  { NULL, }
};

const symbol cc2_codes[] = {
  { "UNC", 0 },  { "unc", 0 },
  { "AEQ", 5 },  { "aeq", 5 },
  { "ANEQ", 4 }, { "aneq", 4 },
  { "AGT", 6 },  { "agt", 6 },
  { "ALT", 3 },  { "alt", 3 },
  { "ALEQ", 7 }, { "aleq", 7 },
  { "AGEQ", 2 }, { "ageq", 2 },
  { "BEQ", 13 }, { "beq", 13 },
  { "BNEQ", 12 },{ "bneq", 12 },
  { "BGT", 14 }, { "bgt", 14 },
  { "BLT", 11 }, { "blt", 11 },
  { "BLEQ", 15 },{ "bleq", 15 },
  { "BGEQ", 10 },{ "bgeq", 10 },
  { NULL },
};

const symbol cc3_codes[] = {
  { "EQ", 0x0000 },  { "eq", 0x0000 },
  { "LT", 0x0100 },  { "lt", 0x0100 },
  { "GT", 0x0200 },  { "gt", 0x0200 },
  { "NEQ", 0x0300 }, { "neq", 0x0300 },
  { "0", 0x0000 }, 
  { "1", 0x0100 },
  { "2", 0x0200 },
  { "3", 0x0300 },
  { "00", 0x0000 }, 
  { "01", 0x0100 },
  { "10", 0x0200 },
  { "11", 0x0300 },
  { NULL },
};

/* FIXME -- also allow decimal digits */
const symbol status_bits[] = {
  /* status register 0 */
  { "TC",  12 },                { "tc",  12 },
  { "C",   11 },                { "c",   11 },
  { "OVA", 10 },                { "ova", 10 },
  { "OVB",  9 },                { "ovb",  9 },
  /* status register 1 */
  { "BRAF",15 },                { "braf",15 },
  { "CPL", 14 },                { "cpl", 14 },
  { "XF",  13 },                { "xf",  13 },
  { "HM",  12 },                { "hm",  12 },
  { "INTM",11 },                { "intm",11 },
  { "OVM",  9 },                { "ovm",  9 },
  { "SXM",  8 },                { "sxm",  8 },
  { "C16",  7 },                { "c16",  7 },
  { "FRCT", 6 },                { "frct", 6 },
  { "CMPT", 5 },                { "cmpt", 5 },
  { NULL },
};

const char *misc_symbols[] = {
  "ARP", "arp",
  "DP",  "dp",
  "ASM", "asm",
  "TS",  "ts",
  NULL
};

/* Due to the way instructions are hashed and scanned in
   gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
   placed 

   Items marked with "PREFER" have been moved prior to a more costly
   instruction with a similar operand format.

   Mnemonics which can take either a predefined symbol or a memory reference
   as an argument are arranged so that the more restrictive (predefined
   symbol) version is checked first (marked "SRC").
*/
const template tic54x_unknown_opcode = 
  { "???",   1,0,0,0x0000, 0x0000, {0}, };
const template tic54x_optab[] = {
  /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
  { "fb",    2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, },
  { "fbd",   2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, },
  { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, },
  { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, },

  { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, },
  { "abs",   1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, },
  { "add",   1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/