m32r-desc.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,384 行 · 第 1/3 页

    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* beqz $src2,$disp16 */
  {
    M32R_INSN_BEQZ, "beqz", "beqz", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bgez $src2,$disp16 */
  {
    M32R_INSN_BGEZ, "bgez", "bgez", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bgtz $src2,$disp16 */
  {
    M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* blez $src2,$disp16 */
  {
    M32R_INSN_BLEZ, "blez", "blez", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bltz $src2,$disp16 */
  {
    M32R_INSN_BLTZ, "bltz", "bltz", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bnez $src2,$disp16 */
  {
    M32R_INSN_BNEZ, "bnez", "bnez", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bl.s $disp8 */
  {
    M32R_INSN_BL8, "bl8", "bl.s", 16,
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* bl.l $disp24 */
  {
    M32R_INSN_BL24, "bl24", "bl.l", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bcl.s $disp8 */
  {
    M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
  },
/* bcl.l $disp24 */
  {
    M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
  },
/* bnc.s $disp8 */
  {
    M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* bnc.l $disp24 */
  {
    M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bne $src1,$src2,$disp16 */
  {
    M32R_INSN_BNE, "bne", "bne", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bra.s $disp8 */
  {
    M32R_INSN_BRA8, "bra8", "bra.s", 16,
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* bra.l $disp24 */
  {
    M32R_INSN_BRA24, "bra24", "bra.l", 32,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* bncl.s $disp8 */
  {
    M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
  },
/* bncl.l $disp24 */
  {
    M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
  },
/* cmp $src1,$src2 */
  {
    M32R_INSN_CMP, "cmp", "cmp", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* cmpi $src2,$simm16 */
  {
    M32R_INSN_CMPI, "cmpi", "cmpi", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* cmpu $src1,$src2 */
  {
    M32R_INSN_CMPU, "cmpu", "cmpu", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* cmpui $src2,$simm16 */
  {
    M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* cmpeq $src1,$src2 */
  {
    M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
    { 0, { (1<<MACH_M32RX), PIPE_OS } }
  },
/* cmpz $src2 */
  {
    M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
    { 0, { (1<<MACH_M32RX), PIPE_OS } }
  },
/* div $dr,$sr */
  {
    M32R_INSN_DIV, "div", "div", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* divu $dr,$sr */
  {
    M32R_INSN_DIVU, "divu", "divu", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* rem $dr,$sr */
  {
    M32R_INSN_REM, "rem", "rem", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* remu $dr,$sr */
  {
    M32R_INSN_REMU, "remu", "remu", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* divh $dr,$sr */
  {
    M32R_INSN_DIVH, "divh", "divh", 32,
    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
  },
/* jc $sr */
  {
    M32R_INSN_JC, "jc", "jc", 16,
    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
  },
/* jnc $sr */
  {
    M32R_INSN_JNC, "jnc", "jnc", 16,
    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
  },
/* jl $sr */
  {
    M32R_INSN_JL, "jl", "jl", 16,
    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* jmp $sr */
  {
    M32R_INSN_JMP, "jmp", "jmp", 16,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* ld $dr,@$sr */
  {
    M32R_INSN_LD, "ld", "ld", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* ld $dr,@($slo16,$sr) */
  {
    M32R_INSN_LD_D, "ld-d", "ld", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* ldb $dr,@$sr */
  {
    M32R_INSN_LDB, "ldb", "ldb", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* ldb $dr,@($slo16,$sr) */
  {
    M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* ldh $dr,@$sr */
  {
    M32R_INSN_LDH, "ldh", "ldh", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* ldh $dr,@($slo16,$sr) */
  {
    M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* ldub $dr,@$sr */
  {
    M32R_INSN_LDUB, "ldub", "ldub", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* ldub $dr,@($slo16,$sr) */
  {
    M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* lduh $dr,@$sr */
  {
    M32R_INSN_LDUH, "lduh", "lduh", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* lduh $dr,@($slo16,$sr) */
  {
    M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* ld $dr,@$sr+ */
  {
    M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* ld24 $dr,$uimm24 */
  {
    M32R_INSN_LD24, "ld24", "ld24", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* ldi8 $dr,$simm8 */
  {
    M32R_INSN_LDI8, "ldi8", "ldi8", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* ldi16 $dr,$hash$slo16 */
  {
    M32R_INSN_LDI16, "ldi16", "ldi16", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* lock $dr,@$sr */
  {
    M32R_INSN_LOCK, "lock", "lock", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* machi $src1,$src2 */
  {
    M32R_INSN_MACHI, "machi", "machi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* machi $src1,$src2,$acc */
  {
    M32R_INSN_MACHI_A, "machi-a", "machi", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* maclo $src1,$src2 */
  {
    M32R_INSN_MACLO, "maclo", "maclo", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* maclo $src1,$src2,$acc */
  {
    M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* macwhi $src1,$src2 */
  {
    M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* macwhi $src1,$src2,$acc */
  {
    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
  },
/* macwlo $src1,$src2 */
  {
    M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* macwlo $src1,$src2,$acc */
  {
    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
  },
/* mul $dr,$sr */
  {
    M32R_INSN_MUL, "mul", "mul", 16,
    { 0, { (1<<MACH_BASE), PIPE_S } }
  },
/* mulhi $src1,$src2 */
  {
    M32R_INSN_MULHI, "mulhi", "mulhi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mulhi $src1,$src2,$acc */
  {
    M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mullo $src1,$src2 */
  {
    M32R_INSN_MULLO, "mullo", "mullo", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mullo $src1,$src2,$acc */
  {
    M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mulwhi $src1,$src2 */
  {
    M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mulwhi $src1,$src2,$acc */
  {
    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
  },
/* mulwlo $src1,$src2 */
  {
    M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mulwlo $src1,$src2,$acc */
  {
    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
  },
/* mv $dr,$sr */
  {
    M32R_INSN_MV, "mv", "mv", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* mvfachi $dr */
  {
    M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mvfachi $dr,$accs */
  {
    M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mvfaclo $dr */
  {
    M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mvfaclo $dr,$accs */
  {
    M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mvfacmi $dr */
  {
    M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mvfacmi $dr,$accs */
  {
    M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mvfc $dr,$scr */
  {
    M32R_INSN_MVFC, "mvfc", "mvfc", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* mvtachi $src1 */
  {
    M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mvtachi $src1,$accs */
  {
    M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mvtaclo $src1 */
  {
    M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* mvtaclo $src1,$accs */
  {
    M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* mvtc $sr,$dcr */
  {
    M32R_INSN_MVTC, "mvtc", "mvtc", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* neg $dr,$sr */
  {
    M32R_INSN_NEG, "neg", "neg", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* nop */
  {
    M32R_INSN_NOP, "nop", "nop", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* not $dr,$sr */
  {
    M32R_INSN_NOT, "not", "not", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* rac */
  {
    M32R_INSN_RAC, "rac", "rac", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* rac $accd,$accs,$imm1 */
  {
    M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* rach */
  {
    M32R_INSN_RACH, "rach", "rach", 16,
    { 0, { (1<<MACH_M32R), PIPE_S } }
  },
/* rach $accd,$accs,$imm1 */
  {
    M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
    { 0, { (1<<MACH_M32RX), PIPE_S } }
  },
/* rte */
  {
    M32R_INSN_RTE, "rte", "rte", 16,
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* seth $dr,$hash$hi16 */
  {
    M32R_INSN_SETH, "seth", "seth", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* sll $dr,$sr */
  {
    M32R_INSN_SLL, "sll", "sll", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* sll3 $dr,$sr,$simm16 */
  {
    M32R_INSN_SLL3, "sll3", "sll3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* slli $dr,$uimm5 */
  {
    M32R_INSN_SLLI, "slli", "slli", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* sra $dr,$sr */
  {
    M32R_INSN_SRA, "sra", "sra", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },
/* sra3 $dr,$sr,$simm16 */
  {
    M32R_INSN_SRA3, "sra3", "sra3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* srai $dr,$uimm5 */
  {
    M32R_INSN_SRAI, "srai", "srai", 16,
    { 0, { (1<<MACH_BASE), PIPE_O } }
  },