m32r-desc.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,384 行 · 第 1/3 页

/* CPU data for m32r.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#include "sysdep.h"
#include <ctype.h>
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "m32r-desc.h"
#include "m32r-opc.h"
#include "opintl.h"
#include "libiberty.h"

/* Attributes.  */

static const CGEN_ATTR_ENTRY bool_attr[] =
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY MACH_attr[] =
{
  { "base", MACH_BASE },
  { "m32r", MACH_M32R },
  { "m32rx", MACH_M32RX },
  { "max", MACH_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY ISA_attr[] =
{
  { "m32r", ISA_M32R },
  { "max", ISA_MAX },
  { 0, 0 }
};

static const CGEN_ATTR_ENTRY PIPE_attr[] =
{
  { "NONE", PIPE_NONE },
  { "O", PIPE_O },
  { "S", PIPE_S },
  { "OS", PIPE_OS },
  { 0, 0 }
};

const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "RELOC", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { "RELOC", &bool_attr[0], &bool_attr[0] },
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
  { "SPECIAL", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
};

/* Instruction set variants.  */

static const CGEN_ISA m32r_cgen_isa_table[] = {
  { "m32r", 32, 32, 16, 32 },
  { 0, 0, 0, 0, 0 }
};

/* Machine variants.  */

static const CGEN_MACH m32r_cgen_mach_table[] = {
  { "m32r", "m32r", MACH_M32R },
  { "m32rx", "m32rx", MACH_M32RX },
  { 0, 0, 0 }
};

static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
{
  { "fp", 13, {0, {0}}, 0, 0 },
  { "lr", 14, {0, {0}}, 0, 0 },
  { "sp", 15, {0, {0}}, 0, 0 },
  { "r0", 0, {0, {0}}, 0, 0 },
  { "r1", 1, {0, {0}}, 0, 0 },
  { "r2", 2, {0, {0}}, 0, 0 },
  { "r3", 3, {0, {0}}, 0, 0 },
  { "r4", 4, {0, {0}}, 0, 0 },
  { "r5", 5, {0, {0}}, 0, 0 },
  { "r6", 6, {0, {0}}, 0, 0 },
  { "r7", 7, {0, {0}}, 0, 0 },
  { "r8", 8, {0, {0}}, 0, 0 },
  { "r9", 9, {0, {0}}, 0, 0 },
  { "r10", 10, {0, {0}}, 0, 0 },
  { "r11", 11, {0, {0}}, 0, 0 },
  { "r12", 12, {0, {0}}, 0, 0 },
  { "r13", 13, {0, {0}}, 0, 0 },
  { "r14", 14, {0, {0}}, 0, 0 },
  { "r15", 15, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD m32r_cgen_opval_gr_names =
{
  & m32r_cgen_opval_gr_names_entries[0],
  19,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
{
  { "psw", 0, {0, {0}}, 0, 0 },
  { "cbr", 1, {0, {0}}, 0, 0 },
  { "spi", 2, {0, {0}}, 0, 0 },
  { "spu", 3, {0, {0}}, 0, 0 },
  { "bpc", 6, {0, {0}}, 0, 0 },
  { "bbpsw", 8, {0, {0}}, 0, 0 },
  { "bbpc", 14, {0, {0}}, 0, 0 },
  { "cr0", 0, {0, {0}}, 0, 0 },
  { "cr1", 1, {0, {0}}, 0, 0 },
  { "cr2", 2, {0, {0}}, 0, 0 },
  { "cr3", 3, {0, {0}}, 0, 0 },
  { "cr4", 4, {0, {0}}, 0, 0 },
  { "cr5", 5, {0, {0}}, 0, 0 },
  { "cr6", 6, {0, {0}}, 0, 0 },
  { "cr7", 7, {0, {0}}, 0, 0 },
  { "cr8", 8, {0, {0}}, 0, 0 },
  { "cr9", 9, {0, {0}}, 0, 0 },
  { "cr10", 10, {0, {0}}, 0, 0 },
  { "cr11", 11, {0, {0}}, 0, 0 },
  { "cr12", 12, {0, {0}}, 0, 0 },
  { "cr13", 13, {0, {0}}, 0, 0 },
  { "cr14", 14, {0, {0}}, 0, 0 },
  { "cr15", 15, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD m32r_cgen_opval_cr_names =
{
  & m32r_cgen_opval_cr_names_entries[0],
  23,
  0, 0, 0, 0
};

static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
{
  { "a0", 0, {0, {0}}, 0, 0 },
  { "a1", 1, {0, {0}}, 0, 0 }
};

CGEN_KEYWORD m32r_cgen_opval_h_accums =
{
  & m32r_cgen_opval_h_accums_entries[0],
  2,
  0, 0, 0, 0
};



/* The hardware table.  */

#define A(a) (1 << CONCAT2 (CGEN_HW_,a))

const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
{
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
  { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
  { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
};

#undef A

/* The instruction field table.  */

#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))

const CGEN_IFLD m32r_cgen_ifld_table[] =
{
  { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
  { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
  { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
  { 0, 0, 0, 0, 0, 0, {0, {0}} }
};

#undef A

/* The operand table.  */

#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)

const CGEN_OPERAND m32r_cgen_operand_table[] =
{
/* pc: program counter */
  { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* sr: source register */
  { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* dr: destination register */
  { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* src1: source register 1 */
  { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* src2: source register 2 */
  { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* scr: source control register */
  { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* dcr: destination control register */
  { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
    { 0, { (1<<MACH_BASE) } }  },
/* simm8: 8 bit signed immediate */
  { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* simm16: 16 bit signed immediate */
  { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* uimm4: 4 bit trap number */
  { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* uimm5: 5 bit shift count */
  { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* uimm16: 16 bit unsigned immediate */
  { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
    { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
/* imm1: 1 bit immediate */
  { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
/* accd: accumulator destination register */
  { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
    { 0, { (1<<MACH_M32RX) } }  },
/* accs: accumulator source register */
  { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
    { 0, { (1<<MACH_M32RX) } }  },
/* acc: accumulator reg (d) */
  { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
    { 0, { (1<<MACH_M32RX) } }  },
/* hash: # prefix */
  { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
    { 0, { (1<<MACH_BASE) } }  },
/* hi16: high 16 bit immediate, sign optional */
  { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
    { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
/* slo16: 16 bit signed immediate, for low() */
  { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
    { 0, { (1<<MACH_BASE) } }  },
/* ulo16: 16 bit unsigned immediate, for low() */
  { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
    { 0, { (1<<MACH_BASE) } }  },
/* uimm24: 24 bit address */
  { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
    { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
/* disp8: 8 bit displacement */
  { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* disp16: 16 bit displacement */
  { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
    { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* disp24: 24 bit displacement */
  { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
    { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
/* condbit: condition bit */
  { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
/* accum: accumulator */
  { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
  { 0, 0, 0, 0, 0, {0, {0}} }
};

#undef A

#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))

/* The instruction table.  */

static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
{
  /* Special null first entry.
     A `num' value of zero is thus invalid.
     Also, the special `invalid' insn resides here.  */
  { 0, 0, 0, 0, {0, {0}} },
/* add $dr,$sr */
  {
    M32R_INSN_ADD, "add", "add", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* add3 $dr,$sr,$hash$slo16 */
  {
    M32R_INSN_ADD3, "add3", "add3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* and $dr,$sr */
  {
    M32R_INSN_AND, "and", "and", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* and3 $dr,$sr,$uimm16 */
  {
    M32R_INSN_AND3, "and3", "and3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* or $dr,$sr */
  {
    M32R_INSN_OR, "or", "or", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* or3 $dr,$sr,$hash$ulo16 */
  {
    M32R_INSN_OR3, "or3", "or3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* xor $dr,$sr */
  {
    M32R_INSN_XOR, "xor", "xor", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* xor3 $dr,$sr,$uimm16 */
  {
    M32R_INSN_XOR3, "xor3", "xor3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* addi $dr,$simm8 */
  {
    M32R_INSN_ADDI, "addi", "addi", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* addv $dr,$sr */
  {
    M32R_INSN_ADDV, "addv", "addv", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* addv3 $dr,$sr,$simm16 */
  {
    M32R_INSN_ADDV3, "addv3", "addv3", 32,
    { 0, { (1<<MACH_BASE), PIPE_NONE } }
  },
/* addx $dr,$sr */
  {
    M32R_INSN_ADDX, "addx", "addx", 16,
    { 0, { (1<<MACH_BASE), PIPE_OS } }
  },
/* bc.s $disp8 */
  {
    M32R_INSN_BC8, "bc8", "bc.s", 16,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
  },
/* bc.l $disp24 */
  {
    M32R_INSN_BC24, "bc24", "bc.l", 32,
    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
  },
/* beq $src1,$src2,$disp16 */
  {
    M32R_INSN_BEQ, "beq", "beq", 32,