changelog

来自「基于4个mips核的noc设计」· 代码 · 共 1,275 行 · 第 1/3 页

	* fr30-desc.h: Partially regenerated to account for changed
	CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
	* m32r-desc.h: Ditto.

2000-05-15  Nick Clifton  <[e-mail]>

	* arm-opc.h: Use upper case for flasg in MSR and MRS
	instructions.  Allow any bit to be set in the field_mask of
	the MSR instruction.

	* arm-dis.c (print_insn_arm): Decode _x and _s bits of the
	field_mask of an MSR instruction.

2000-05-11  Thomas de Lellis  <[e-mail]>

	* arm-opc.h: Disassembly of thumb ldsb/ldsh
	instructions changed to ldrsb/ldrsh.

2000-05-11  Ulf Carlsson  <[e-mail]>

	* mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit
	target addresses for 'jal' and 'j'.

2000-05-10  Geoff Keating  <[e-mail]>

	* ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes
	also available in common mode when powerpc syntax is being used.

2000-05-08  Alan Modra  <[e-mail]>

	* m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args.
	(dummy_print_address): Ditto.

2000-05-04  Timothy Wall  <[e-mail]>

	* tic54x-opc.c: New.
	* tic54x-dis.c: New.
	* disassemble.c (disassembler): Add ARCH_tic54x.
	* configure.in: Added tic54x target.
	* configure: Ditto.
	* Makefile.am: Add tic54x dependencies.
	* Makefile.in: Ditto.

2000-05-03  J.T. Conklin  <[e-mail]>

	* ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for
	vector unit operands.
	(VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector
	unit instruction formats.
	(PPCVEC): New macro, mask for vector instructions.
	(powerpc_operands): Add table entries for above operand types.
	(powerpc_opcodes): Add table entries for vector instructions.

	* ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask.
	(print_insn_little_powerpc): Likewise.
	(print_insn_powerpc): Prepend 'v' when printing vector registers.

2000-04-24  Clinton Popetz  <[e-mail]>

	* configure.in: Add bfd_powerpc_64_arch.
	* disassemble.c (disassembler): Use print_insn_big_powerpc for
	64 bit code.

2000-04-24  Nick Clifton  <[e-mail]>

	* fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow
	field.

2000-04-23  Denis Chertykov  <[e-mail]>

	* avr-dis.c (reg_fmul_d): New. Extract destination register from
	FMUL instruction.
	(reg_fmul_r): New. Extract source register from FMUL instruction.
	(reg_muls_d): New. Extract destination register from MULS instruction.
	(reg_muls_r): New. Extract source register from MULS instruction.
	(reg_movw_d): New. Extract destination register from MOVW instruction.
	(reg_movw_r): New. Extract source register from MOVW instruction.
	(print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU,
	EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions.

2000-04-22  Timothy Wall  <[e-mail]>

	* ia64-gen.c (general): Add an ordered table of primary
	opcode names, as well as priority fields to disassembly data
	structures to enforce a preferred disassembly format based on the
	ordering of the opcode tables.
	(load_insn_classes): Show a useful message if IC tables are missing.
	(load_depfile): Ditto.
	* ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to
	distinguish preferred disassembly.
	* ia64-opc-f.c: Reorder some insn for preferred disassembly
	format.  Fix incorrect flag on fma.s/fma.s.s0.
	* ia64-opc.c: Scan *all* disassembly matches and use the one with
	the highest priority.
	* ia64-opc-b.c: Use more abbreviations.
	* ia64-asmtab.c: Regenerate.

2000-04-21  Jason Eckhardt  <[e-mail]>

	* hppa-dis.c (extract_16): New function.
	(print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of
	new operand types l,y,&,fe,fE,fx.

2000-04-21  Richard Henderson  <[e-mail]>
	    David Mosberger  <[e-mail]>
	    Timothy Wall <[e-mail]>
	    Bob Manson  <[e-mail]>
	    Jim Wilson  <[e-mail]>

	* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
	(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
	ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
	ia64-asmtab.c.
	(ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
	(ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
	ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
	* Makefile.in: Rebuild.
	* configure Rebuild.
	* configure.in (bfd_ia64_arch): New target.
	* disassemble.c (ARCH_ia64): Define.
	(disassembler): Support ARCH_ia64.
	* ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
	ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
	ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
	ia64-war.tbl, ia64-waw.tbl: New files.

2000-04-20  Alexandre Oliva  <[e-mail]>

	* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.
	(disassemble): Use them.

2000-04-14  Alan Modra  <[e-mail]>

	* sysdep.h: Include "ansidecl.h" not <ansidecl.h>
	* Makefile.am: Update dependencies.
	* Makefile.in: Regenerate.

2000-04-14  Michael Sokolov  <[e-mail]>

	* a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c,
	avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c,
	disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c,
	i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c,
	m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c,
	mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c,
	ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c,
	tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c,
	w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h.  Remove
	ansidecl.h as sysdep.h includes it.

2000-04-7  Andrew Cagney  <[e-mail]>

	* configure.in (WARN_CFLAGS): Set to -W -Wall by default.  Add
	--enable-build-warnings option.
	* Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions.
	* Makefile.in, configure: Re-generate.

2000-04-05  J"orn Rennecke <[e-mail]>

	* sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs.
	stc GBR,@-<REG_N> is available for arch_sh1_up.
	Group parallel processing insn with identical mnemonics together.
	Make three-operand psha / pshl come first.

2000-04-05  J"orn Rennecke <[e-mail]>

	* sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4.
	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.
	(sh_arg_type): Add A_PC.
	(sh_table): Update entries using immediates.  Add repeat.
	* sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4.
	Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}.  Add REPEAT.

2000-04-04  Alan Modra  <[e-mail]>

	* po/opcodes.pot: Regenerate.

	* Makefile.am (MKDEP): Use gcc -MM rather than mkdep.
	(DEP): Quote when passing vars to sub-make.  Add warning message
	to end.
	(DEP1): Rewrite for "gcc -MM".
	(CLEANFILES): Add DEP2.
	Update dependencies.
	* Makefile.in: Regenerate.

2000-04-03  Denis Chertykov  <[e-mail]>

	* avr-dis.c: Syntax cleanup.
	(add0fff): Print the pc relative address as a signed number.
	(add03f8): Likewise.

2000-04-01  Ian Lance Taylor  <[e-mail]>

	* disassemble.c (disassembler_usage): Don't use a prototype.  Mark
	the parameter ATTRIBUTE_UNUSED.
	* ppc-opc.c: Add ATTRIBUTE_UNUSED as needed.

2000-04-01  Alexandre Oliva  <[e-mail]>

	* m10300-opc.c: SP-based offsets are always unsigned.

2000-03-29  Thomas de Lellis  <[e-mail]>

	* arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal"
	[branch always] instead of "undefined".

2000-03-27  Nick Clifton  <[e-mail]>

	* d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of
	short instructions, from end of list of long instructions.

2000-03-27  Ian Lance Taylor  <[e-mail]>

	* Makefile.am (CFILES): Add avr-dis.c.
	(ALL_MACHINES): Add avr-dis.lo.

2000-03-27  Alan Modra  <[e-mail]>

	* avr-dis.c (add0fff, add03f8): Don't use structure bitfields to
	truncate integers.
	(print_insn_avr): Call function via pointer in K&R compatible way.
	(dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204,
	add0fff, add03f8): Convert to old style function declaration and
	add prototype.
	(avrdis_opcode): Add prototype.

2000-03-27  Denis Chertykov  <[e-mail]>

	* avr-dis.c: New file.  AVR disassembler.
	* configure.in (bfd_avr_arch): New architecture support.
	* disassemble.c: Likewise.
	* configure: Regenerate.

2000-03-06  J"oern Rennecke <[e-mail]>

	* sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement.

2000-03-02  J"orn Rennecke <[e-mail]>

	* d30v-dis.c (print_insn): Remove d*i hacks.  Use per-operand
	flag to determine if operand is pc-relative.
	* d30v-opc.c:
	(d30v_format_table):
	(REL6S3): Renamed from IMM6S3.
	Added flag OPERAND_PCREL.
	(REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
	added flag OPERAND_PCREL.
	(IMM12S3U): Replaced with REL12S3.
	(SHORT_D2, LONG_D): Delay target is pc-relative.
	(SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
	Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
	using the REL* operands.
	(LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
	(SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
	LONG_Db, using REL* operands.
	(SHORT_U, SHORT_A5S): Removed stray alternatives.
	(d30v_opcode_table): Use new *r formats.

2000-02-28  Nick Clifton  <[e-mail]>

	* m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with
	'signed_overflow_ok_p'.

2000-02-27  Eli Zaretskii  <[e-mail]>

	* Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the
	name of the libtool directory.
	* Makefile.in: Rebuild.

2000-02-24  Nick Clifton  <[e-mail]>

	* cgen-opc.c (cgen_set_signed_overflow_ok): New function.
	(cgen_clear_signed_overflow_ok): New function.
	(cgen_signed_overflow_ok_p): New function.

2000-02-23  Andrew Haley  <[e-mail]>

	* m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c,
	m32r-ibld.c, m32r-opc.h: Rebuild.

2000-02-23  Linas Vepstas <[e-mail]>

	* i370-dis.c, i370-opc.c: New.

	* disassemble.c (ARCH_i370): Define.
	(disassembler): Handle it.

	* Makefile.am: Add support for Linux/IBM 370.
	* configure.in: Likewise.

	* Makefile.in: Regenerate.
	* configure: Likewise.

2000-02-22  Chandra Chavva   <[e-mail]>

	* d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to
	ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel
	procedure.

2000-02-22  Andrew Haley  <[e-mail]>

	* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
	force gp32 to zero.
	* mips-opc.c (G6): New define.
	(mips_builtin_op): Add "move" definition for -gp32.

2000-02-22  Ian Lance Taylor  <[e-mail]>

	From Grant Erickson <[e-mail]>:
	* ppc-opc.c: Correct dcread--it takes 3 arguments, not 2.

2000-02-21  Alan Modra  <[e-mail]>

	* dis-buf.c (buffer_read_memory): Change `length' param and all int
	vars to unsigned.

2000-02-17 J"orn Rennecke <[e-mail]>

	* sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions.
	(print_insn_ppi): Likewise.
	(print_insn_shx): Use info->mach to select appropriate insn set.
	Add support for sh-dsp.  Remove FD_REG_N support.
	* sh-opc.h (sh_nibble_type): Add new values for sh-dsp support.
	(sh_arg_type): Likewise.  Remove FD_REG_N.
	(sh_dsp_reg_nums): New enum.
	(arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros.
	(arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise.
	(arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise.
	(arch_sh3_dsp_up): Likewise.
	(sh_opcode_info): New field: arch.
	(sh_table): Split up insn with FD_REG_N into ones with F_REG_N and
	D_REG_N.  Fill in arch field.  Add sh-dsp insns.

2000-02-14  Fernando Nasser  <[e-mail]>

	* arm-dis.c: Change flavor name from atpcs-special to
	special-atpcs to prevent name conflict in gdb.
	(get_arm_regname_num_options, set_arm_regname_option,
	get_arm_regnames): New functions.  API to access the several
	flavor of register names.  Note: Used by gdb.
	(print_insn_thumb): Use the register name entry from the currently
	selected flavor for LR and PC.

2000-02-10  Nick Clifton  <[e-mail]>

	* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
	classes.
	(mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
	"mulsh.h" instructions.
	* mcore-dis.c (imsk array): Add masks for MULSH and OPSR
	classes.
	(print_insn_mcore): Add support for little endian targets.
	Add support for MULSH and OPSR classes.

2000-02-07  Nick Clifton  <[e-mail]>

	* arm-dis.c (parse_arm_diassembler_option): Rename again.
	Previous delat did not take.

2000-02-03  Timothy Wall  <[e-mail]>

	* dis-buf.c (buffer_read_memory):  Use octets_per_byte field
	to adjust target address bounds checking and calculate the
	appropriate octet offset into data.

2000-01-27  Nick Clifton  <[e-mail]>

	* arm-dis.c: (parse_disassembler_option): Rename to
	parse_arm_disassembler_option and allow to be exported.

	* disassemble.c (disassembler_usage): New function: Print out any
	target specific disassembler options.
	Call arm_disassembler_options() if the ARM architecture is being
	supported.

	* arm-dis.c (NUM_ELEM): Define this macro if not already
	defined.
	(arm_regname): New struct type for ARM register names.
	(arm_toggle_regnames): Delete.
	(parse_disassembler_option): Use register name structure.
	(print_insn): New function: Combines duplicate code found in
	print_insn_big_arm and print_insn_little_arm.
	(print_insn_big_arm): Call print_insn.
	(print_insn_little_arm): Call print_insn.
	(print_arm_disassembler_options): Display list of supported,
	ARM specific disassembler options.

2000-01-27  Thomas de Lellis  <[e-mail]>

	* arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the
	ARM_STT_16BIT flag as Thumb code symbols.

	* arm-dis.c (printf_insn_little_arm): Ditto.

2000-01-25  Thomas de Lellis  <[e-mail]>

	* arm-dis.c (printf_insn_thumb): Prevent double dumping
	of raw thumb instructions.

2000-01-20  Nick Clifton  <[e-mail]>

	* mcore-opc.h (mcore_table): Add "add" as an alias for "addu".

2000-01-03  Nick Clifton  <[e-mail]>

	* arm-dis.c (streq): New macro.
	(strneq): New macro.
	(force_thumb): ew local variable.
	(parse_disassembler_option): New function: Parse a single, ARM
	specific disassembler command line switch.
	(parse_disassembler_option): Call parse_disassembler_option to
	parse individual command line switches.
	(print_insn_big_arm): Check force_thumb.
	(print_insn_little_arm): Check force_thumb.

For older changes see ChangeLog-9899

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