m32r-opc.c

来自「基于4个mips核的noc设计」· C语言 代码 · 共 1,687 行 · 第 1/3 页

    & ifmt_cmp, { 0x3040 }
  },
/* machi $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3040 }
  },
/* maclo $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3050 }
  },
/* maclo $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3050 }
  },
/* macwhi $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3060 }
  },
/* macwhi $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3060 }
  },
/* macwlo $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3070 }
  },
/* macwlo $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3070 }
  },
/* mul $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x1060 }
  },
/* mulhi $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3000 }
  },
/* mulhi $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3000 }
  },
/* mullo $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3010 }
  },
/* mullo $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3010 }
  },
/* mulwhi $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3020 }
  },
/* mulwhi $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3020 }
  },
/* mulwlo $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x3030 }
  },
/* mulwlo $src1,$src2,$acc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
    & ifmt_machi_a, { 0x3030 }
  },
/* mv $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x1080 }
  },
/* mvfachi $dr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), 0 } },
    & ifmt_mvfachi, { 0x50f0 }
  },
/* mvfachi $dr,$accs */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
    & ifmt_mvfachi_a, { 0x50f0 }
  },
/* mvfaclo $dr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), 0 } },
    & ifmt_mvfachi, { 0x50f1 }
  },
/* mvfaclo $dr,$accs */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
    & ifmt_mvfachi_a, { 0x50f1 }
  },
/* mvfacmi $dr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), 0 } },
    & ifmt_mvfachi, { 0x50f2 }
  },
/* mvfacmi $dr,$accs */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
    & ifmt_mvfachi_a, { 0x50f2 }
  },
/* mvfc $dr,$scr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
    & ifmt_mvfc, { 0x1090 }
  },
/* mvtachi $src1 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), 0 } },
    & ifmt_mvtachi, { 0x5070 }
  },
/* mvtachi $src1,$accs */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
    & ifmt_mvtachi_a, { 0x5070 }
  },
/* mvtaclo $src1 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), 0 } },
    & ifmt_mvtachi, { 0x5071 }
  },
/* mvtaclo $src1,$accs */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
    & ifmt_mvtachi_a, { 0x5071 }
  },
/* mvtc $sr,$dcr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
    & ifmt_mvtc, { 0x10a0 }
  },
/* neg $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x30 }
  },
/* nop */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x7000 }
  },
/* not $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0xb0 }
  },
/* rac */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x5090 }
  },
/* rac $accd,$accs,$imm1 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
    & ifmt_rac_dsi, { 0x5090 }
  },
/* rach */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x5080 }
  },
/* rach $accd,$accs,$imm1 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
    & ifmt_rac_dsi, { 0x5080 }
  },
/* rte */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x10d6 }
  },
/* seth $dr,$hash$hi16 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
    & ifmt_seth, { 0xd0c00000 }
  },
/* sll $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x1040 }
  },
/* sll3 $dr,$sr,$simm16 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
    & ifmt_addv3, { 0x90c00000 }
  },
/* slli $dr,$uimm5 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
    & ifmt_slli, { 0x5040 }
  },
/* sra $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x1020 }
  },
/* sra3 $dr,$sr,$simm16 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
    & ifmt_addv3, { 0x90a00000 }
  },
/* srai $dr,$uimm5 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
    & ifmt_slli, { 0x5020 }
  },
/* srl $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x1000 }
  },
/* srl3 $dr,$sr,$simm16 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
    & ifmt_addv3, { 0x90800000 }
  },
/* srli $dr,$uimm5 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
    & ifmt_slli, { 0x5000 }
  },
/* st $src1,@$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x2040 }
  },
/* st $src1,@($slo16,$src2) */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
    & ifmt_st_d, { 0xa0400000 }
  },
/* stb $src1,@$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x2000 }
  },
/* stb $src1,@($slo16,$src2) */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
    & ifmt_st_d, { 0xa0000000 }
  },
/* sth $src1,@$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x2020 }
  },
/* sth $src1,@($slo16,$src2) */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
    & ifmt_st_d, { 0xa0200000 }
  },
/* st $src1,@+$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x2060 }
  },
/* st $src1,@-$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x2070 }
  },
/* sub $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x20 }
  },
/* subv $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x0 }
  },
/* subx $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_add, { 0x10 }
  },
/* trap $uimm4 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (UIMM4), 0 } },
    & ifmt_trap, { 0x10f0 }
  },
/* unlock $src1,@$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x2050 }
  },
/* satb $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_satb, { 0x80600300 }
  },
/* sath $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_satb, { 0x80600200 }
  },
/* sat $dr,$sr */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
    & ifmt_satb, { 0x80600000 }
  },
/* pcmpbz $src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC2), 0 } },
    & ifmt_cmpz, { 0x370 }
  },
/* sadd */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x50e4 }
  },
/* macwu1 $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x50b0 }
  },
/* msblo $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x50d0 }
  },
/* mulwu1 $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x50a0 }
  },
/* maclh1 $src1,$src2 */
  {
    { 0, 0, 0, 0 },
    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
    & ifmt_cmp, { 0x50c0 }
  },
/* sc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x7401 }
  },
/* snc */
  {
    { 0, 0, 0, 0 },
    { { MNEM, 0 } },
    & ifmt_nop, { 0x7501 }
  },
};

#undef A
#undef MNEM
#undef OPERAND
#undef OP

/* Formats for ALIAS macro-insns.  */

#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]

static const CGEN_IFMT ifmt_bc8r = {
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
};

static const CGEN_IFMT ifmt_bc24r = {
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
};

static const CGEN_IFMT ifmt_bl8r = {
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
};

static const CGEN_IFMT ifmt_bl24r = {
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
};

static const CGEN_IFMT ifmt_bcl8r = {
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
};

static const CGEN_IFMT ifmt_bcl24r = {
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
};

static const CGEN_IFMT ifmt_bnc8r = {
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
};

static const CGEN_IFMT ifmt_bnc24r = {
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
};

static const CGEN_IFMT ifmt_bra8r = {
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
};

static const CGEN_IFMT ifmt_bra24r = {
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
};

static const CGEN_IFMT ifmt_bncl8r = {
  16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
};

static const CGEN_IFMT ifmt_bncl24r = {
  32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
};

static const CGEN_IFMT ifmt_ld_2 = {
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_ld_d2 = {
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldb_2 = {
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldb_d2 = {
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldh_2 = {
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldh_d2 = {
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldub_2 = {
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldub_d2 = {
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
};

static const CGEN_IFMT ifmt_lduh_2 = {
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_lduh_d2 = {
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
};

static const CGEN_IFMT ifmt_pop = {
  16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldi8a = {
  16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
};

static const CGEN_IFMT ifmt_ldi16a = {
  32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
};

static const CGEN_IFMT ifmt_rac_d = {
  16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
};

static const CGEN_IFMT ifmt_rac_ds = {
  16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
};

static const CGEN_IFMT ifmt_rach_d = {
  16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
};

static const CGEN_IFMT ifmt_rach_ds = {
  16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
};

static const CGEN_IFMT ifmt_st_2 = {
  16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
};

static const CGEN_IFMT ifmt_st_d2 = {
  32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
};