cris-opc.c

基于4个mips核的noc设计

/* cris-opc.c -- Table of opcodes for the CRIS processor.
   Copyright 2000 Free Software Foundation, Inc.
   Contributed by Axis Communications AB, Lund, Sweden.
   Originally written for GAS 1.38.1 by Mikael Asker.
   Reorganized by Hans-Peter Nilsson.

This file is part of GAS, GDB and the GNU binutils.

GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2, or (at your
option) any later version.

GAS, GDB, and GNU binutils are distributed in the hope that they will be
useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#include "opcode/cris.h"

#ifndef NULL
#define NULL (0)
#endif

const struct cris_spec_reg
cris_spec_regs[] =
{
  {"p0",  0,  1, 0,		   NULL},
  {"vr",  1,  1, 0,		   NULL},
  {"p1",  1,  1, 0,		   NULL},
  {"p2",  2,  1, cris_ver_warning, NULL},
  {"p3",  3,  1, cris_ver_warning, NULL},
  {"p4",  4,  2, 0,		   NULL},
  {"ccr", 5,  2, 0,		   NULL},
  {"p5",  5,  2, 0,		   NULL},
  {"dcr0",6,  2, cris_ver_v0_3,	   NULL},
  {"p6",  6,  2, cris_ver_v0_3,	   NULL},
  {"dcr1/mof", 7, 4, cris_ver_v10p,
   "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
  {"dcr1/mof", 7, 2, cris_ver_v0_3,
   "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
  {"mof", 7,  4, cris_ver_v10p,	   NULL},
  {"dcr1",7,  2, cris_ver_v0_3,	   NULL},
  {"p7",  7,  4, cris_ver_v10p,	   NULL},
  {"p7",  7,  2, cris_ver_v0_3,	   NULL},
  {"p8",  8,  4, 0,		   NULL},
  {"ibr", 9,  4, 0,		   NULL},
  {"p9",  9,  4, 0,		   NULL},
  {"irp", 10, 4, 0,		   NULL},
  {"p10", 10, 4, 0,		   NULL},
  {"srp", 11, 4, 0,		   NULL},
  {"p11", 11, 4, 0,		   NULL},
  /* For disassembly use only.  Accept at assembly with a warning.  */
  {"bar/dtp0", 12, 4, cris_ver_warning,
   "Ambiguous register `bar/dtp0' specified"},
  {"bar", 12, 4, cris_ver_v8p,	   NULL},
  {"dtp0",12, 4, cris_ver_v0_3,	   NULL},
  {"p12", 12, 4, 0,		   NULL},
  /* For disassembly use only.  Accept at assembly with a warning.  */
  {"dccr/dtp1",13, 4, cris_ver_warning,
   "Ambiguous register `dccr/dtp1' specified"},
  {"dccr",13, 4, cris_ver_v8p,	   NULL},
  {"dtp1",13, 4, cris_ver_v0_3,	   NULL},
  {"p13", 13, 4, 0,		   NULL},
  {"brp", 14, 4, cris_ver_v3p,	   NULL},
  {"p14", 14, 4, cris_ver_v3p,	   NULL},
  {"usp", 15, 4, cris_ver_v10p,	   NULL},
  {"p15", 15, 4, cris_ver_v10p,	   NULL},
  {NULL, 0, 0, NULL}
};

/* All CRIS opcodes are 16 bits.

   - The match component is a mask saying which bits must match a
     particular opcode in order for an instruction to be an instance
     of that opcode.

   - The args component is a string containing characters symbolically
     matching the operands of an instruction.  Used for both assembly
     and disassembly.

     Operand-matching characters:
     B	Not really an operand.  It causes a "BDAP -size,SP" prefix to be
	output for the PUSH alias-instructions and recognizes a
	push-prefix at disassembly.  Must be followed by a R or P letter.
     !	Non-match pattern, will not match if there's a prefix insn.
     b	Non-matching operand, used for branches with 16-bit
	displacement. Only recognized by the disassembler.
     c	5-bit unsigned immediate in bits <4:0>.
     C	4-bit unsigned immediate in bits <3:0>.
     D	General register in bits <15:12> and <3:0>.
     f	List of flags in bits <15:12> and <3:0>.
     i	6-bit signed immediate in bits <5:0>.
     I	6-bit unsigned immediate in bits <5:0>.
     M	Size modifier (B, W or D) for CLEAR instructions.
     m	Size modifier (B, W or D) in bits <5:4>
     o	[-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
	branch instructions.
     O	[-128..127] offset in bits <7:0>.  Also matches a comma and a
	general register after the expression.  Used only for the BDAP
	prefix insn.
     P	Special register in bits <15:12>.
     p	Indicates that the insn is a prefix insn.  Must be first
	character.
     R	General register in bits <15:12>.
     r	General register in bits <3:0>.
     S	Source operand in bit <10> and a prefix; a 3-operand prefix
	without side-effect.
     s	Source operand in bits <10> and <3:0>, optionally with a
	side-effect prefix.
     x	Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
     y	Like 's' but do not allow an integer at assembly.
     z	Size modifier (B or W) in bit <4>.  */


/* Please note the order of the opcodes in this table is significant.
   The assembler requires that all instances of the same mnemonic must
   be consecutive.  If they aren't, the assembler might not recognize
   them, or may indicate and internal error.

   The disassembler should not normally care about the order of the
   opcodes, but will prefer an earlier alternative if the "match-score"
   (see cris-dis.c) is computed as equal.

   It should not be significant for proper execution that this table is
   in alphabetical order, but please follow that convention for an easy
   overview.  */

const struct cris_opcode
cris_opcodes[] =
{
  {"abs",     0x06B0, 0x0940,		  "r,R",     0, SIZE_NONE,     0,
   cris_abs_op},

  {"add",     0x0600, 0x09c0,		  "m r,R",   0, SIZE_NONE,     0,
   cris_reg_mode_add_sub_cmp_and_or_move_op},

  {"add",     0x0A00, 0x01c0,		  "m s,R",   0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"add",     0x0A00, 0x01c0,		  "m S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"add",     0x0a00, 0x05c0,		  "m S,R,r", 0, SIZE_NONE,     0,
   cris_three_operand_add_sub_cmp_and_or_op},

  {"addi",    0x0500, 0x0Ac0,		  "x,r",     0, SIZE_NONE,     0,
   cris_addi_op},

  {"addq",    0x0200, 0x0Dc0,		  "I,R",     0, SIZE_NONE,     0,
   cris_quick_mode_add_sub_op},

  {"adds",    0x0420, 0x0Bc0,		  "z r,R",   0, SIZE_NONE,     0,
   cris_reg_mode_add_sub_cmp_and_or_move_op},

  {"adds",    0x0820, 0x03c0,		  "z s,R",   0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"adds",    0x0820, 0x03c0,		  "z S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"adds",    0x0820, 0x07c0,		  "z S,R,r", 0, SIZE_NONE,     0,
   cris_three_operand_add_sub_cmp_and_or_op},

  {"addu",    0x0400, 0x0be0,		  "z r,R",   0, SIZE_NONE,     0,
   cris_reg_mode_add_sub_cmp_and_or_move_op},

  {"addu",    0x0800, 0x03e0,		  "z s,R",   0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"addu",    0x0800, 0x03e0,		  "z S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"addu",    0x0800, 0x07e0,		  "z S,R,r", 0, SIZE_NONE,     0,
   cris_three_operand_add_sub_cmp_and_or_op},

  {"and",     0x0700, 0x08C0,		  "m r,R",   0, SIZE_NONE,     0,
   cris_reg_mode_add_sub_cmp_and_or_move_op},

  {"and",     0x0B00, 0x00C0,		  "m s,R",   0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"and",     0x0B00, 0x00C0,		  "m S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"and",     0x0B00, 0x04C0,		  "m S,R,r", 0, SIZE_NONE,     0,
   cris_three_operand_add_sub_cmp_and_or_op},

  {"andq",    0x0300, 0x0CC0,		  "i,R",     0, SIZE_NONE,     0,
   cris_quick_mode_and_cmp_move_or_op},

  {"asr",     0x0780, 0x0840,		  "m r,R",   0, SIZE_NONE,     0,
   cris_asr_op},

  {"asrq",    0x03a0, 0x0c40,		  "c,R",     0, SIZE_NONE,     0,
   cris_asrq_op},

  {"ax",      0x15B0, 0xEA4F,		  "",	     0, SIZE_NONE,     0,
   cris_ax_ei_setf_op},

  /* FIXME: Should use branch #defines.  */
  {"b",	      0x0dff, 0x0200,		  "b",	     1, SIZE_NONE,     0,
   cris_sixteen_bit_offset_branch_op},

  {"ba",
   BA_QUICK_OPCODE,
   0x0F00+(0xF-CC_A)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bcc",
   BRANCH_QUICK_OPCODE+CC_CC*0x1000,
   0x0f00+(0xF-CC_CC)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bcs",
   BRANCH_QUICK_OPCODE+CC_CS*0x1000,
   0x0f00+(0xF-CC_CS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bdap",
   BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD,    0,
   cris_bdap_prefix},

  {"bdap",
   BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",	     0, SIZE_NONE,     0,
   cris_quick_mode_bdap_prefix},

  {"beq",
   BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
   0x0f00+(0xF-CC_EQ)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  /* This is deliberately put before "bext" to trump it, even though not
     in alphabetical order.  */
  {"bwf",
   BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
   0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
   cris_ver_v10p,
   cris_eight_bit_offset_branch_op},

  {"bext",
   BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
   0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
   cris_ver_v0_3,
   cris_eight_bit_offset_branch_op},

  {"bge",
   BRANCH_QUICK_OPCODE+CC_GE*0x1000,
   0x0f00+(0xF-CC_GE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bgt",
   BRANCH_QUICK_OPCODE+CC_GT*0x1000,
   0x0f00+(0xF-CC_GT)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bhi",
   BRANCH_QUICK_OPCODE+CC_HI*0x1000,
   0x0f00+(0xF-CC_HI)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bhs",
   BRANCH_QUICK_OPCODE+CC_HS*0x1000,
   0x0f00+(0xF-CC_HS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"biap", BIAP_OPCODE, BIAP_Z_BITS,	  "pm r,R",  0, SIZE_NONE,     0,
   cris_biap_prefix},

  {"ble",
   BRANCH_QUICK_OPCODE+CC_LE*0x1000,
   0x0f00+(0xF-CC_LE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"blo",
   BRANCH_QUICK_OPCODE+CC_LO*0x1000,
   0x0f00+(0xF-CC_LO)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bls",
   BRANCH_QUICK_OPCODE+CC_LS*0x1000,
   0x0f00+(0xF-CC_LS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"blt",
   BRANCH_QUICK_OPCODE+CC_LT*0x1000,
   0x0f00+(0xF-CC_LT)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bmi",
   BRANCH_QUICK_OPCODE+CC_MI*0x1000,
   0x0f00+(0xF-CC_MI)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bmod",    0x0ab0, 0x0140,		  "s,R",     0, SIZE_FIX_32,
   cris_ver_sim,
   cris_not_implemented_op},

  {"bmod",    0x0ab0, 0x0140,		  "S,D",     0, SIZE_NONE,
   cris_ver_sim,
   cris_not_implemented_op},

  {"bmod",    0x0ab0, 0x0540,		  "S,R,r",   0, SIZE_NONE,
   cris_ver_sim,
   cris_not_implemented_op},

  {"bne",
   BRANCH_QUICK_OPCODE+CC_NE*0x1000,
   0x0f00+(0xF-CC_NE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bound",   0x05c0, 0x0A00,		  "m r,R",   0, SIZE_NONE,     0,
   cris_two_operand_bound_op},
  {"bound",   0x09c0, 0x0200,		  "m s,R",   0, SIZE_FIELD,    0,
   cris_two_operand_bound_op},
  {"bound",   0x09c0, 0x0200,		  "m S,D",   0, SIZE_NONE,     0,
   cris_two_operand_bound_op},
  {"bound",   0x09c0, 0x0600,		  "m S,R,r", 0, SIZE_NONE,     0,
   cris_three_operand_bound_op},
  {"bpl",
   BRANCH_QUICK_OPCODE+CC_PL*0x1000,
   0x0f00+(0xF-CC_PL)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"break",   0xe930, 0x16c0,		  "C",	     0, SIZE_NONE,
   cris_ver_v3p,
   cris_break_op},

  {"bstore",  0x0af0, 0x0100,		  "s,R",     0, SIZE_FIX_32,
   cris_ver_warning,
   cris_not_implemented_op},

  {"bstore",  0x0af0, 0x0100,		  "S,D",     0, SIZE_NONE,
   cris_ver_warning,
   cris_not_implemented_op},

  {"bstore",  0x0af0, 0x0500,		  "S,R,r",   0, SIZE_NONE,
   cris_ver_warning,
   cris_not_implemented_op},

  {"btst",    0x04F0, 0x0B00,		  "r,R",     0, SIZE_NONE,     0,
   cris_btst_nop_op},
  {"btstq",   0x0380, 0x0C60,		  "c,R",     0, SIZE_NONE,     0,
   cris_btst_nop_op},
  {"bvc",
   BRANCH_QUICK_OPCODE+CC_VC*0x1000,
   0x0f00+(0xF-CC_VC)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"bvs",
   BRANCH_QUICK_OPCODE+CC_VS*0x1000,
   0x0f00+(0xF-CC_VS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
   cris_eight_bit_offset_branch_op},

  {"clear",   0x0670, 0x3980,		  "M r",     0, SIZE_NONE,     0,
   cris_reg_mode_clear_op},

  {"clear",   0x0A70, 0x3180,		  "M y",     0, SIZE_NONE,     0,
   cris_none_reg_mode_clear_test_op},

  {"clear",   0x0A70, 0x3180,		  "M S",     0, SIZE_NONE,     0,
   cris_none_reg_mode_clear_test_op},

  {"clearf",  0x05F0, 0x0A00,		  "f",	     0, SIZE_NONE,     0,
   cris_clearf_di_op},

  {"cmp",     0x06C0, 0x0900,		  "m r,R",   0, SIZE_NONE,     0,
   cris_reg_mode_add_sub_cmp_and_or_move_op},

  {"cmp",     0x0Ac0, 0x0100,		  "m s,R",   0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"cmp",     0x0Ac0, 0x0100,		  "m S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"cmpq",    0x02C0, 0x0D00,		  "i,R",     0, SIZE_NONE,     0,
   cris_quick_mode_and_cmp_move_or_op},

  {"cmps",    0x08e0, 0x0300,		  "z s,R",   0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"cmps",    0x08e0, 0x0300,		  "z S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"cmpu",    0x08c0, 0x0320,		  "z s,R" ,  0, SIZE_FIELD,    0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"cmpu",    0x08c0, 0x0320,		  "z S,D",   0, SIZE_NONE,     0,
   cris_none_reg_mode_add_sub_cmp_and_or_move_op},

  {"di",      0x25F0, 0xDA0F,		  "",	     0, SIZE_NONE,     0,
   cris_clearf_di_op},

  {"dip",     DIP_OPCODE, DIP_Z_BITS,	  "ps",	     0, SIZE_FIX_32,   0,
   cris_dip_prefix},

  {"div",     0x0980, 0x0640,		  "m R,r",   0, SIZE_FIELD,    0,
   cris_not_implemented_op},

  {"dstep",   0x06f0, 0x0900,		  "r,R",     0, SIZE_NONE,     0,
   cris_dstep_logshift_mstep_neg_not_op},

  {"ei",      0x25B0, 0xDA4F,		  "",	     0, SIZE_NONE,     0,
   cris_ax_ei_setf_op},

  {"jbrc",    0x69b0, 0x9640,		  "r",	     0, SIZE_NONE,
   cris_ver_v8p,
   cris_reg_mode_jump_op},

  {"jbrc",    0x6930, 0x92c0,		  "s",	     0, SIZE_FIX_32,
   cris_ver_v8p,
   cris_none_reg_mode_jump_op},

  {"jbrc",    0x6930, 0x92c0,		  "S",	     0, SIZE_NONE,
   cris_ver_v8p,
   cris_none_reg_mode_jump_op},

  {"jir",     0xA9b0, 0x5640,		  "r",	     0, SIZE_NONE,     0,
   cris_reg_mode_jump_op},

  {"jir",     0xA930, 0x52c0,		  "s",	     0, SIZE_FIX_32,   0,
   cris_none_reg_mode_jump_op},

  {"jir",     0xA930, 0x52c0,		  "S",	     0, SIZE_NONE,     0,
   cris_none_reg_mode_jump_op},

  {"jirc",    0x29b0, 0xd640,		  "r",	     0, SIZE_NONE,
   cris_ver_v8p,
   cris_reg_mode_jump_op},

  {"jirc",    0x2930, 0xd2c0,		  "s",	     0, SIZE_FIX_32,
   cris_ver_v8p,
   cris_none_reg_mode_jump_op},

  {"jirc",    0x2930, 0xd2c0,		  "S",	     0, SIZE_NONE,
   cris_ver_v8p,
   cris_none_reg_mode_jump_op},

  {"jsr",     0xB9b0, 0x4640,		  "r",	     0, SIZE_NONE,     0,