tic80-opc.c

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  int rtnval = -1;

  while (low <= high)
    {
      middle = (low + high) / 2;
      cmp = strcasecmp (name, tic80_predefined_symbols[middle].name);
      if (cmp < 0)
	{
	  high = middle - 1;
	}
      else if (cmp > 0)
	{
	  low = middle + 1;
	}
      else 
	{
	  pdsp = &tic80_predefined_symbols[middle];
	  if ((class == 0) || (class & PDS_VALUE (pdsp)))
	    {
	      rtnval = PDS_VALUE (pdsp);
	    }
	  /* For now we assume that there are no duplicate names */
	  break;
	}
    }
  return (rtnval);
}

/* This function takes a value VAL and finds a matching predefined
   symbol that is in the operand class specified by CLASS.  If CLASS
   is zero, the first matching symbol is returned. */

const char *
tic80_value_to_symbol (val, class)
     int val;
     int class;
{
  const struct predefined_symbol *pdsp;
  int ival;
  char *name;

  name = NULL;
  for (pdsp = tic80_predefined_symbols;
       pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols;
       pdsp++)
    {
      ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
      if (ival == val)
	{
	  if ((class == 0) || (class & PDS_VALUE (pdsp)))
	    {
	      /* Found the desired match */
	      name = PDS_NAME (pdsp);
	      break;
	    }
	}
    }
  return (name);
}

/* This function returns a pointer to the next symbol in the predefined
   symbol table after PDSP, or NULL if PDSP points to the last symbol.  If
   PDSP is NULL, it returns the first symbol in the table.  Thus it can be
   used to walk through the table by first calling it with NULL and then
   calling it with each value it returned on the previous call, until it
   returns NULL. */

const struct predefined_symbol *
tic80_next_predefined_symbol (pdsp)
     const struct predefined_symbol *pdsp;
{
  if (pdsp == NULL)
    {
      pdsp = tic80_predefined_symbols;
    }
  else if (pdsp >= tic80_predefined_symbols &&
	   pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1)
    {
      pdsp++;
    }
  else
    {
      pdsp = NULL;
    }
  return (pdsp);
}



/* The operands table.  The fields are:

	bits, shift, insertion function, extraction function, flags
 */

const struct tic80_operand tic80_operands[] =
{

  /* The zero index is used to indicate the end of the list of operands.  */

#define UNUSED (0)
  { 0, 0, 0, 0, 0 },

  /* Short signed immediate value in bits 14-0. */

#define SSI (UNUSED + 1)
  { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },

  /* Short unsigned immediate value in bits 14-0 */

#define SUI (SSI + 1)
  { 15, 0, NULL, NULL, 0 },

  /* Short unsigned bitfield in bits 14-0.  We distinguish this
     from a regular unsigned immediate value only for the convenience
     of the disassembler and the user. */

#define SUBF (SUI + 1)
  { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },

  /* Long signed immediate in following 32 bit word */

#define LSI (SUBF + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },

  /* Long unsigned immediate in following 32 bit word */

#define LUI (LSI + 1)
  { 32, 0, NULL, NULL, 0 },

  /* Long unsigned bitfield in following 32 bit word.  We distinguish
     this from a regular unsigned immediate value only for the
     convenience of the disassembler and the user. */

#define LUBF (LUI + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },

  /* Single precision floating point immediate in following 32 bit
     word. */

#define SPFI (LUBF + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },

  /* Register in bits 4-0 */

#define REG_0 (SPFI + 1)
  { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },

  /* Even register in bits 4-0 */

#define REG_0_E (REG_0 + 1)
  { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },

  /* Register in bits 26-22 */

#define REG_22 (REG_0_E + 1)
  { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },

  /* Even register in bits 26-22 */

#define REG_22_E (REG_22 + 1)
  { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },

  /* Register in bits 31-27 */

#define REG_DEST (REG_22_E + 1)
  { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },

  /* Even register in bits 31-27 */

#define REG_DEST_E (REG_DEST + 1)
  { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },

  /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB)
     and bit 11 (LSB) */
  /* FIXME!  Needs to use functions to insert and extract the register
     number in bits 16 and 11. */

#define REG_FPA (REG_DEST_E + 1)
  { 0, 0, NULL, NULL, TIC80_OPERAND_FPA },

  /* Short signed PC word offset in bits 14-0 */

#define OFF_SS_PC (REG_FPA + 1)
  { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },

  /* Long signed PC word offset in following 32 bit word */

#define OFF_SL_PC (OFF_SS_PC + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },

  /* Short signed base relative byte offset in bits 14-0 */

#define OFF_SS_BR (OFF_SL_PC + 1)
  { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },

  /* Long signed base relative byte offset in following 32 bit word */

#define OFF_SL_BR (OFF_SS_BR + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },

  /* Long signed base relative byte offset in following 32 bit word
     with optional ":s" modifier flag in bit 11 */

#define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },

  /* BITNUM in bits 31-27 */

#define BITNUM (OFF_SL_BR_SCALED + 1)
  { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },

  /* Condition code in bits 31-27 */

#define CC (BITNUM + 1)
  { 5, 27, NULL, NULL, TIC80_OPERAND_CC },

  /* Control register number in bits 14-0 */

#define CR_SI (CC + 1)
  { 15, 0, NULL, NULL, TIC80_OPERAND_CR },

  /* Control register number in next 32 bit word */

#define CR_LI (CR_SI + 1)
  { 32, 0, NULL, NULL, TIC80_OPERAND_CR },

  /* A base register in bits 26-22, enclosed in parens */

#define REG_BASE (CR_LI + 1)
  { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },

  /* A base register in bits 26-22, enclosed in parens, with optional ":m"
     flag in bit 17 (short immediate instructions only) */

#define REG_BASE_M_SI (REG_BASE + 1)
  { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },

  /* A base register in bits 26-22, enclosed in parens, with optional ":m"
   flag in bit 15 (long immediate and register instructions only) */

#define REG_BASE_M_LI (REG_BASE_M_SI + 1)
  { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },

  /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */