as.texinfo

基于4个mips核的noc设计

@item -W
@itemx --no-warn
Suppress warning messages.

@item --fatal-warnings
Treat warnings as errors.

@item --warn
Don't suppress warning messages or treat them as errors.

@item -w
Ignored.

@item -x
Ignored.

@item -Z
Generate an object file even after errors.

@item -- | @var{files} @dots{}
Standard input, or source files to assemble.

@end table

@ifset ARC
The following options are available when @value{AS} is configured for
an ARC processor.

@table @code
@item -marc[5|6|7|8]
This option selects the core processor variant.
@item -EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
@end table
@end ifset

@ifset ARM
The following options are available when @value{AS} is configured for the ARM
processor family.

@table @code
@item -m[arm][1|2|3|6|7|8|9][...] 
Specify which ARM processor variant is the target.
@item -m[arm]v[2|2a|3|3m|4|4t|5|5t]
Specify which ARM architecture variant is used by the target.
@item -mthumb | -mall
Enable or disable Thumb only instruction decoding.
@item -mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu
Select which Floating Point architecture is the target.
@item -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi
Select which procedure calling convention is in use.
@item -EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
@item -mthumb-interwork
Specify that the code has been generated with interworking between Thumb and
ARM code in mind.
@item -k
Specify that PIC code has been generated.
@end table
@end ifset

@ifset D10V
The following options are available when @value{AS} is configured for
a D10V processor.
@table @code
@cindex D10V optimization
@cindex optimization, D10V
@item -O
Optimize output by parallelizing instructions.
@end table
@end ifset

@ifset D30V
The following options are available when @value{AS} is configured for a D30V
processor.
@table @code
@cindex D30V optimization
@cindex optimization, D30V
@item -O
Optimize output by parallelizing instructions.

@cindex D30V nops
@item -n
Warn when nops are generated.

@cindex D30V nops after 32-bit multiply
@item -N
Warn when a nop after a 32-bit multiply instruction is generated.
@end table
@end ifset

@ifset I960
The following options are available when @value{AS} is configured for the
Intel 80960 processor.

@table @code
@item -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Specify which variant of the 960 architecture is the target.

@item -b
Add code to collect statistics about branches taken.

@item -no-relax
Do not alter compare-and-branch instructions for long displacements;
error if necessary.

@end table
@end ifset

@ifset M32R
The following options are available when @value{AS} is configured for the
Mitsubishi M32R series.

@table @code

@item --m32rx
Specify which processor in the M32R family is the target.  The default
is normally the M32R, but this option changes it to the M32RX.

@item --warn-explicit-parallel-conflicts or --Wp
Produce warning messages when questionable parallel constructs are
encountered. 

@item --no-warn-explicit-parallel-conflicts or --Wnp
Do not produce warning messages when questionable parallel constructs are 
encountered. 

@end table
@end ifset

@ifset M680X0
The following options are available when @value{AS} is configured for the
Motorola 68000 series.

@table @code

@item -l
Shorten references to undefined symbols, to one word instead of two.

@item -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060
@itemx | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -mcpu32 | -m5200
Specify what processor in the 68000 family is the target.  The default
is normally the 68020, but this can be changed at configuration time.

@item -m68881 | -m68882 | -mno-68881 | -mno-68882
The target machine does (or does not) have a floating-point coprocessor.
The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
the basic 68000 is not compatible with the 68881, a combination of the
two can be specified, since it's possible to do emulation of the
coprocessor instructions with the main processor.

@item -m68851 | -mno-68851
The target machine does (or does not) have a memory-management
unit coprocessor.  The default is to assume an MMU for 68020 and up.

@end table
@end ifset

@ifset PJ
The following options are available when @value{AS} is configured for
a picoJava processor.

@table @code

@cindex PJ endianness
@cindex endianness, PJ
@cindex big endian output, PJ
@item -mb
Generate ``big endian'' format output.

@cindex little endian output, PJ
@item -ml
Generate ``little endian'' format output.

@end table
@end ifset

@ifset M68HC11
The following options are available when @value{AS} is configured for the
Motorola 68HC11 or 68HC12 series.

@table @code

@item -m68hc11 | -m68hc12
Specify what processor is the target.  The default is
defined by the configuration option when building the assembler.

@item --force-long-branchs
Relative branches are turned into absolute ones. This concerns
conditional branches, unconditional branches and branches to a
sub routine.

@item -S | --short-branchs
Do not turn relative branchs into absolute ones
when the offset is out of range.

@item --strict-direct-mode
Do not turn the direct addressing mode into extended addressing mode
when the instruction does not support direct addressing mode.

@item --print-insn-syntax
Print the syntax of instruction in case of error.

@item --print-opcodes
print the list of instructions with syntax and then exit.

@item --generate-example
print an example of instruction for each possible instruction and then exit.
This option is only useful for testing @code{@value{AS}}.

@end table
@end ifset

@ifset SPARC
The following options are available when @code{@value{AS}} is configured
for the SPARC architecture:

@table @code
@item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
@itemx -Av8plus | -Av8plusa | -Av9 | -Av9a
Explicitly select a variant of the SPARC architecture.

@samp{-Av8plus} and @samp{-Av8plusa} select a 32 bit environment.
@samp{-Av9} and @samp{-Av9a} select a 64 bit environment.

@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
UltraSPARC extensions.

@item -xarch=v8plus | -xarch=v8plusa
For compatibility with the Solaris v9 assembler.  These options are
equivalent to -Av8plus and -Av8plusa, respectively.

@item -bump
Warn when the assembler switches to another architecture.
@end table
@end ifset

@ifset TIC54X
The following options are available when @value{AS} is configured for the 'c54x
architecture. 

@table @code
@item -mfar-mode
Enable extended addressing mode.  All addresses and relocations will assume
extended addressing (usually 23 bits).
@item -mcpu=@var{CPU_VERSION}
Sets the CPU version being compiled for.
@item -merrors-to-file @var{FILENAME}
Redirect error output to a file, for broken systems which don't support such
behaviour in the shell.
@end table
@end ifset

@ifset MIPS
The following options are available when @value{AS} is configured for
a MIPS processor.

@table @code
@item -G @var{num}
This option sets the largest size of an object that can be referenced
implicitly with the @code{gp} register.  It is only accepted for targets that
use ECOFF format, such as a DECstation running Ultrix.  The default value is 8.

@cindex MIPS endianness
@cindex endianness, MIPS
@cindex big endian output, MIPS
@item -EB
Generate ``big endian'' format output.

@cindex little endian output, MIPS
@item -EL
Generate ``little endian'' format output.

@cindex MIPS ISA
@item -mips1
@itemx -mips2
@itemx -mips3
@itemx -mips4
@itemx -mips32
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, and @samp{-mips3} to the @sc{r4000}
processor.
@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
processors, respectively.

@item -m4650
@itemx -no-m4650
Generate code for the MIPS @sc{r4650} chip.  This tells the assembler to accept
the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
instructions around accesses to the @samp{HI} and @samp{LO} registers.
@samp{-no-m4650} turns off this option.

@item -mcpu=@var{CPU}
Generate code for a particular MIPS cpu.  It is exactly equivalent to
@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
understood.

@cindex emulation
@item --emulation=@var{name}
This option causes @code{@value{AS}} to emulate @code{@value{AS}} configured
for some other target, in all respects, including output format (choosing
between ELF and ECOFF only), handling of pseudo-opcodes which may generate
debugging information or store symbol table information, and default
endianness.  The available configuration names are: @samp{mipsecoff},
@samp{mipself}, @samp{mipslecoff}, @samp{mipsbecoff}, @samp{mipslelf},
@samp{mipsbelf}.  The first two do not alter the default endianness from that
of the primary target for which the assembler was configured; the others change
the default to little- or big-endian as indicated by the @samp{b} or @samp{l}
in the name.  Using @samp{-EB} or @samp{-EL} will override the endianness
selection in any case.

This option is currently supported only when the primary target
@code{@value{AS}} is configured for is a MIPS ELF or ECOFF target.
Furthermore, the primary target or others specified with
@samp{--enable-targets=@dots{}} at configuration time must include support for
the other format, if both are to be available.  For example, the Irix 5
configuration includes support for both.

Eventually, this option will support more configurations, with more
fine-grained control over the assembler's behavior, and will be supported for
more processors.

@item -nocpp
@code{@value{AS}} ignores this option.  It is accepted for compatibility with
the native tools.

@need 900
@item --trap
@itemx --no-trap
@itemx --break
@itemx --no-break
Control how to deal with multiplication overflow and division by zero.
@samp{--trap} or @samp{--no-break} (which are synonyms) take a trap exception
(and only work for Instruction Set Architecture level 2 and higher);
@samp{--break} or @samp{--no-trap} (also synonyms, and the default) take a
break exception.
@end table
@end ifset

@ifset MCORE
The following options are available when @value{AS} is configured for
an MCore processor.

@table @code
@item -jsri2bsr
@itemx -nojsri2bsr
Enable or disable the JSRI to BSR transformation.  By default this is enabled.
The command line option @samp{-nojsri2bsr} can be used to disable it.

@item -sifilter
@itemx -nosifilter
Enable or disable the silicon filter behaviour.  By default this is disabled.
The default can be overridden by the @samp{-sifilter} command line option.

@item -relax
Alter jump instructions for long displacements.

@item -mcpu=[210|340]
Select the cpu type on the target hardware.  This controls which instructions
can be assembled.

@item -EB
Assemble for a big endian target.

@item -EL
Assemble for a little endian target.

@end table
@end ifset

@menu
* Manual::                      Structure of this Manual
* GNU Assembler::               The GNU Assembler
* Object Formats::              Object File Formats
* Command Line::                Command Line
* Input Files::                 Input Files
* Object::                      Output (Object) File
* Errors::                      Error and Warning Messages
@end menu

@node Manual
@section Structure of this Manual

@cindex manual, structure and purpose
This manual is intended to describe what you need to know to use
@sc{gnu} @code{@value{AS}}.  We cover the syntax expected in source files, including
notation for symbols, constants, and expressions; the directives that
@code{@value{AS}} understands; and of course how to invoke @code{@value{AS}}.