📄 tc-arm.c
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{"SPSR", false, PSR_c | PSR_f}, {"SPSR_all", false, PSR_c | PSR_f}, {"CPSR_flg", true, PSR_f}, {"CPSR_f", true, PSR_f}, {"SPSR_flg", false, PSR_f}, {"SPSR_f", false, PSR_f}, {"CPSR_c", true, PSR_c}, {"CPSR_ctl", true, PSR_c}, {"SPSR_c", false, PSR_c}, {"SPSR_ctl", false, PSR_c}, {"CPSR_x", true, PSR_x}, {"CPSR_s", true, PSR_s}, {"SPSR_x", false, PSR_x}, {"SPSR_s", false, PSR_s}, /* Combinations of flags. */ {"CPSR_fs", true, PSR_f | PSR_s}, {"CPSR_fx", true, PSR_f | PSR_x}, {"CPSR_fc", true, PSR_f | PSR_c}, {"CPSR_sf", true, PSR_s | PSR_f}, {"CPSR_sx", true, PSR_s | PSR_x}, {"CPSR_sc", true, PSR_s | PSR_c}, {"CPSR_xf", true, PSR_x | PSR_f}, {"CPSR_xs", true, PSR_x | PSR_s}, {"CPSR_xc", true, PSR_x | PSR_c}, {"CPSR_cf", true, PSR_c | PSR_f}, {"CPSR_cs", true, PSR_c | PSR_s}, {"CPSR_cx", true, PSR_c | PSR_x}, {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x}, {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c}, {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s}, {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c}, {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s}, {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x}, {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x}, {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c}, {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f}, {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c}, {"CPSR_scf", true, PSR_s | PSR_c | PSR_f}, {"CPSR_scx", true, PSR_s | PSR_c | PSR_x}, {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s}, {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c}, {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f}, {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c}, {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f}, {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s}, {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s}, {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x}, {"CPSR_csf", true, PSR_c | PSR_s | PSR_f}, {"CPSR_csx", true, PSR_c | PSR_s | PSR_x}, {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f}, {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s}, {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c}, {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x}, {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c}, {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s}, {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x}, {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s}, {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c}, {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x}, {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c}, {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f}, {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x}, {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f}, {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c}, {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s}, {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c}, {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f}, {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s}, {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f}, {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x}, {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s}, {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x}, {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f}, {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s}, {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f}, {"SPSR_fs", false, PSR_f | PSR_s}, {"SPSR_fx", false, PSR_f | PSR_x}, {"SPSR_fc", false, PSR_f | PSR_c}, {"SPSR_sf", false, PSR_s | PSR_f}, {"SPSR_sx", false, PSR_s | PSR_x}, {"SPSR_sc", false, PSR_s | PSR_c}, {"SPSR_xf", false, PSR_x | PSR_f}, {"SPSR_xs", false, PSR_x | PSR_s}, {"SPSR_xc", false, PSR_x | PSR_c}, {"SPSR_cf", false, PSR_c | PSR_f}, {"SPSR_cs", false, PSR_c | PSR_s}, {"SPSR_cx", false, PSR_c | PSR_x}, {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x}, {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c}, {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s}, {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c}, {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s}, {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x}, {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x}, {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c}, {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f}, {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c}, {"SPSR_scf", false, PSR_s | PSR_c | PSR_f}, {"SPSR_scx", false, PSR_s | PSR_c | PSR_x}, {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s}, {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c}, {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f}, {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c}, {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f}, {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s}, {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s}, {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x}, {"SPSR_csf", false, PSR_c | PSR_s | PSR_f}, {"SPSR_csx", false, PSR_c | PSR_s | PSR_x}, {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f}, {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s}, {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c}, {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x}, {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c}, {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s}, {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x}, {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s}, {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c}, {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x}, {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c}, {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f}, {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x}, {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f}, {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c}, {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s}, {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c}, {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f}, {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s}, {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f}, {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x}, {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s}, {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x}, {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f}, {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s}, {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},};/* Functions called by parser. *//* ARM instructions. */static void do_arit PARAMS ((char *, unsigned long));static void do_cmp PARAMS ((char *, unsigned long));static void do_mov PARAMS ((char *, unsigned long));static void do_ldst PARAMS ((char *, unsigned long));static void do_ldmstm PARAMS ((char *, unsigned long));static void do_branch PARAMS ((char *, unsigned long));static void do_swi PARAMS ((char *, unsigned long));/* Pseudo Op codes. */static void do_adr PARAMS ((char *, unsigned long));static void do_adrl PARAMS ((char *, unsigned long));static void do_nop PARAMS ((char *, unsigned long));/* ARM 2. */static void do_mul PARAMS ((char *, unsigned long));static void do_mla PARAMS ((char *, unsigned long));/* ARM 3. */static void do_swap PARAMS ((char *, unsigned long));/* ARM 6. */static void do_msr PARAMS ((char *, unsigned long));static void do_mrs PARAMS ((char *, unsigned long));/* ARM 7M. */static void do_mull PARAMS ((char *, unsigned long));/* ARM THUMB. */static void do_bx PARAMS ((char *, unsigned long));/* ARM_EXT_XScale. */static void do_mia PARAMS ((char *, unsigned long));static void do_mar PARAMS ((char *, unsigned long));static void do_mra PARAMS ((char *, unsigned long));static void do_pld PARAMS ((char *, unsigned long));static void do_ldrd PARAMS ((char *, unsigned long));/* ARM_EXT_V5. */static void do_blx PARAMS ((char *, unsigned long));static void do_bkpt PARAMS ((char *, unsigned long));static void do_clz PARAMS ((char *, unsigned long));static void do_lstc2 PARAMS ((char *, unsigned long));static void do_cdp2 PARAMS ((char *, unsigned long));static void do_co_reg2 PARAMS ((char *, unsigned long));static void do_t_blx PARAMS ((char *));static void do_t_bkpt PARAMS ((char *));/* ARM_EXT_V5E. */static void do_smla PARAMS ((char *, unsigned long));static void do_smlal PARAMS ((char *, unsigned long));static void do_smul PARAMS ((char *, unsigned long));static void do_qadd PARAMS ((char *, unsigned long));static void do_co_reg2c PARAMS ((char *, unsigned long));/* Coprocessor Instructions. */static void do_cdp PARAMS ((char *, unsigned long));static void do_lstc PARAMS ((char *, unsigned long));static void do_co_reg PARAMS ((char *, unsigned long));static void do_fp_ctrl PARAMS ((char *, unsigned long));static void do_fp_ldst PARAMS ((char *, unsigned long));static void do_fp_ldmstm PARAMS ((char *, unsigned long));static void do_fp_dyadic PARAMS ((char *, unsigned long));static void do_fp_monadic PARAMS ((char *, unsigned long));static void do_fp_cmp PARAMS ((char *, unsigned long));static void do_fp_from_reg PARAMS ((char *, unsigned long));static void do_fp_to_reg PARAMS ((char *, unsigned long));static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));static int arm_reg_parse PARAMS ((char **));static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));static int add_to_lit_pool PARAMS ((void));static unsigned validate_immediate PARAMS ((unsigned));static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));static int validate_offset_imm PARAMS ((unsigned int, int));static void opcode_select PARAMS ((int));static void end_of_line PARAMS ((char *));static int reg_required_here PARAMS ((char **, int));static int psr_required_here PARAMS ((char **));static int co_proc_number PARAMS ((char **));static int cp_opc_expr PARAMS ((char **, int, int));static int cp_reg_required_here PARAMS ((char **, int));static int fp_reg_required_here PARAMS ((char **, int));static int cp_address_offset PARAMS ((char **));static int cp_address_required_here PARAMS ((char **));static int my_get_float_expression PARAMS ((char **));static int skip_past_comma PARAMS ((char **));static int walk_no_bignums PARAMS ((symbolS *));static int negate_data_op PARAMS ((unsigned long *, unsigned long));static int data_op2 PARAMS ((char **));static int fp_op2 PARAMS ((char **));static long reg_list PARAMS ((char **));static void thumb_load_store PARAMS ((char *, int, int));static int decode_shift PARAMS ((char **, int));static int ldst_extend PARAMS ((char **, int));static void thumb_add_sub PARAMS ((char *, int));static void insert_reg PARAMS ((int));static void thumb_shift PARAMS ((char *, int));static void thumb_mov_compare PARAMS ((char *, int));static void set_constant_flonums PARAMS ((void));static valueT md_chars_to_number PARAMS ((char *, int));static void insert_reg_alias PARAMS ((char *, int));static void output_inst PARAMS ((void));#ifdef OBJ_ELFstatic bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));#endif/* ARM instructions take 4bytes in the object file, Thumb instructions take 2: */#define INSN_SIZE 4/* LONGEST_INST is the longest basic instruction name without conditions or flags. ARM7M has 4 of length 5. El Segundo has one basic instruction name of length 7 (SMLALxy). */#define LONGEST_INST 7struct asm_opcode{ /* Basic string to match. */ CONST char * template; /* Basic instruction code. */ unsigned long value; /* Compulsory suffix that must follow conds. If "", then the instruction is not conditional and must have no suffix. */ CONST char * comp_suffix; /* Bits to toggle if flag 'n' set. */ CONST struct asm_flg * flags; /* Which CPU variants this exists for. */ unsigned long variants; /* Function to call to parse args. */ void (* parms) PARAMS ((char *, unsigned long));};static CONST struct asm_opcode insns[] ={/* Intel XScale extensions to ARM V5 ISA. */ {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia}, {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar}, {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra}, {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld}, {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd}, {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd},/* ARM Instructions. */ {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit}, {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit}, {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit}, {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit}, {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit}, {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit}, {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit}, {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit}, {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit}, {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit}, {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp}, {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp}, {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp}, {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp}, {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov}, {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov}, {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst}, {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst}, {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm}, {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm}, {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},#ifdef TE_WINCE {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch}, {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},#else {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch}, {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},#endif/* Pseudo ops. */ {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr}, {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl}, {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},/* ARM 2 multiplies. */ {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul}, {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},/* ARM 3 - swp instructions. */ {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},/* ARM 6 Coprocessor instructions. */ {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs}, {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},/* ScottB: our code uses 0x0128f000 for msr. NickC: but this is wrong because the bits 16 through 19 are handled by the PSR_xxx defines above. *//* ARM 7M long multiplies - need signed/unsigned flags! */ {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull}, {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},/* ARM THUMB interworking. */ {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx},/* Floating point instructions. */ {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl}, {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl}, {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl}, {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl}, {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst}, {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst}, {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm}, {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm}, {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic}, {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic}, {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp}, {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},/* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not be an optional suffix, but part of the instruction. To be compatible, we accept either. */ {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp}, {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp}, {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg}, {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},/* Generic copressor instructions. */ {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp}, {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc}, {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc}, {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg}, {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},/* ARM ISA extension 5. *//* Note: blx is actually 2 opcodes, so the .value is set dynamically. And it's sometimes conditional and sometimes not. */ {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx}, {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz}, {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt}, {"ldc2", 0xfc100000, "", cplong_flag, ARM_EXT_V5, do_lstc2}, {"stc2", 0xfc000000, "", cplong_flag, ARM_EXT_V5, do_lstc2}, {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2}, {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2}, {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2},/* ARM ISA extension 5E, El Segundo. */ {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla}, {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla}, {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla}, {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla}, {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla}, {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla}, {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal}, {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal}, {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal}, {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal}, {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul}, {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul}, {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul}, {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul}, {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul}, {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul}, {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd}, {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd}, {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd}, {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd}, {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c}, {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},};/* Defines for various bits that we will want to toggle. */⌨️ 快捷键说明
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