tc-mips.c

基于4个mips核的noc设计

/* tc-mips.c -- assemble code for a MIPS chip.
   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
   Free Software Foundation, Inc.
   Contributed by the OSF and Ralph Campbell.
   Written by Keith Knowles and Ralph Campbell, working independently.
   Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
   Support.

   This file is part of GAS.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
   02111-1307, USA.  */

#include "as.h"
#include "config.h"
#include "subsegs.h"

#include <ctype.h>

#ifdef USE_STDARG
#include <stdarg.h>
#endif
#ifdef USE_VARARGS
#include <varargs.h>
#endif

#include "opcode/mips.h"
#include "itbl-ops.h"

#ifdef DEBUG
#define DBG(x) printf x
#else
#define DBG(x)
#endif

#ifdef OBJ_MAYBE_ELF
/* Clean up namespace so we can include obj-elf.h too.  */
static int mips_output_flavor PARAMS ((void));
static int mips_output_flavor () { return OUTPUT_FLAVOR; }
#undef OBJ_PROCESS_STAB
#undef OUTPUT_FLAVOR
#undef S_GET_ALIGN
#undef S_GET_SIZE
#undef S_SET_ALIGN
#undef S_SET_SIZE
#undef obj_frob_file
#undef obj_frob_file_after_relocs
#undef obj_frob_symbol
#undef obj_pop_insert
#undef obj_sec_sym_ok_for_reloc
#undef OBJ_COPY_SYMBOL_ATTRIBUTES

#include "obj-elf.h"
/* Fix any of them that we actually care about.  */
#undef OUTPUT_FLAVOR
#define OUTPUT_FLAVOR mips_output_flavor()
#endif

#if defined (OBJ_ELF)
#include "elf/mips.h"
#endif

#ifndef ECOFF_DEBUGGING
#define NO_ECOFF_DEBUGGING
#define ECOFF_DEBUGGING 0
#endif

#include "ecoff.h"

#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
static char *mips_regmask_frag;
#endif

#define AT  1
#define TREG 24
#define PIC_CALL_REG 25
#define KT0 26
#define KT1 27
#define GP  28
#define SP  29
#define FP  30
#define RA  31

#define ILLEGAL_REG (32)

/* Allow override of standard little-endian ECOFF format.  */

#ifndef ECOFF_LITTLE_FORMAT
#define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
#endif

extern int target_big_endian;

/* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
   32 bit ABI.  This has no meaning for ECOFF.
   Note that the default is always 32 bit, even if "configured" for
   64 bit [e.g. --target=mips64-elf].  */
static int mips_64;

/* The default target format to use.  */

const char *
mips_target_format ()
{
  switch (OUTPUT_FLAVOR)
    {
    case bfd_target_aout_flavour:
      return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
    case bfd_target_ecoff_flavour:
      return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
    case bfd_target_coff_flavour:
      return "pe-mips";
    case bfd_target_elf_flavour:
#ifdef TE_TMIPS
      /* This is traditional mips */
      return (target_big_endian
	      ? (mips_64 ? "elf64-tradbigmips" : "elf32-tradbigmips")
	      : (mips_64 ? "elf64-tradlittlemips" : "elf32-tradlittlemips"));
#else
      return (target_big_endian
	      ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips")
	      : (mips_64 ? "elf64-littlemips" : "elf32-littlemips"));
#endif
    default:
      abort ();
      return NULL;
    }
}

/* The name of the readonly data section.  */
#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
			    ? ".data" \
			    : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
			    ? ".rdata" \
			    : OUTPUT_FLAVOR == bfd_target_coff_flavour \
			    ? ".rdata" \
			    : OUTPUT_FLAVOR == bfd_target_elf_flavour \
			    ? ".rodata" \
			    : (abort (), ""))

/* This is the set of options which may be modified by the .set
   pseudo-op.  We use a struct so that .set push and .set pop are more
   reliable.  */

struct mips_set_options
{
  /* MIPS ISA (Instruction Set Architecture) level.  This is set to -1
     if it has not been initialized.  Changed by `.set mipsN', and the
     -mipsN command line option, and the default CPU.  */
  int isa;
  /* Whether we are assembling for the mips16 processor.  0 if we are
     not, 1 if we are, and -1 if the value has not been initialized.
     Changed by `.set mips16' and `.set nomips16', and the -mips16 and
     -nomips16 command line options, and the default CPU.  */
  int mips16;
  /* Non-zero if we should not reorder instructions.  Changed by `.set
     reorder' and `.set noreorder'.  */
  int noreorder;
  /* Non-zero if we should not permit the $at ($1) register to be used
     in instructions.  Changed by `.set at' and `.set noat'.  */
  int noat;
  /* Non-zero if we should warn when a macro instruction expands into
     more than one machine instruction.  Changed by `.set nomacro' and
     `.set macro'.  */
  int warn_about_macros;
  /* Non-zero if we should not move instructions.  Changed by `.set
     move', `.set volatile', `.set nomove', and `.set novolatile'.  */
  int nomove;
  /* Non-zero if we should not optimize branches by moving the target
     of the branch into the delay slot.  Actually, we don't perform
     this optimization anyhow.  Changed by `.set bopt' and `.set
     nobopt'.  */
  int nobopt;
  /* Non-zero if we should not autoextend mips16 instructions.
     Changed by `.set autoextend' and `.set noautoextend'.  */
  int noautoextend;
};

/* This is the struct we use to hold the current set of options.  Note
   that we must set the isa field to ISA_UNKNOWN and the mips16 field to
   -1 to indicate that they have not been initialized.  */

static struct mips_set_options mips_opts =
{
  ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0
};

/* These variables are filled in with the masks of registers used.
   The object format code reads them and puts them in the appropriate
   place.  */
unsigned long mips_gprmask;
unsigned long mips_cprmask[4];

/* MIPS ISA we are using for this output file.  */
static int file_mips_isa = ISA_UNKNOWN;

/* The CPU type we are using for this output file.  */
static int mips_cpu = CPU_UNKNOWN;

/* The argument of the -mabi= flag.  */
static char * mips_abi_string = 0;

/* Wether we should mark the file EABI64 or EABI32.  */
static int mips_eabi64 = 0;

/* If they asked for mips1 or mips2 and a cpu that is
   mips3 or greater, then mark the object file 32BITMODE.  */
static int mips_32bitmode = 0;

/* True if -mgp32 was passed.  */
static int mips_gp32 = 0;

/* Some ISA's have delay slots for instructions which read or write
   from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
   Return true if instructions marked INSN_LOAD_COPROC_DELAY,
   INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
   delay slot in this ISA.  The uses of this macro assume that any
   ISA that has delay slots for one of these, has them for all.  They
   also assume that ISAs which don't have delays for these insns, don't
   have delays for the INSN_LOAD_MEMORY_DELAY instructions either.  */
#define ISA_HAS_COPROC_DELAYS(ISA) (        \
   (ISA) == ISA_MIPS1                       \
   || (ISA) == ISA_MIPS2                    \
   || (ISA) == ISA_MIPS3                    \
   )

/*  Return true if ISA supports 64 bit gp register instructions.  */
#define ISA_HAS_64BIT_REGS(ISA) (    \
   (ISA) == ISA_MIPS3                \
   || (ISA) == ISA_MIPS4             \
   || (ISA) == ISA_MIPS5             \
   || (ISA) == ISA_MIPS64            \
   )

/* Whether the processor uses hardware interlocks to protect
   reads from the HI and LO registers, and thus does not
   require nops to be inserted.

   FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
   -mcpu=FOO schedules for FOO, but still produces code that meets the
   requirements of MIPS ISA I.  For example, it won't generate any
   FOO-specific instructions, and it will still assume that any
   scheduling hazards described in MIPS ISA I are there, even if FOO
   has interlocks.  -mFOO gives GCC permission to generate code that
   will only run on a FOO; it will generate FOO-specific instructions,
   and assume interlocks provided by a FOO.

   However, GAS currently doesn't make this distinction; before Jan 28
   1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
   assumptions.  The GCC driver passes these flags through to GAS, so
   if GAS actually does anything that doesn't meet MIPS ISA I with
   -mFOO, then GCC's -mcpu=FOO flag isn't going to work.

   And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
   which seems senseless --- why generate code which will only run on
   a FOO, but schedule for something else?

   So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.

   -- Jim Blandy <[e-mail]> */

#define hilo_interlocks (mips_cpu == CPU_R4010                       \
                         )

/* Whether the processor uses hardware interlocks to protect reads
   from the GPRs, and thus does not require nops to be inserted.  */
#define gpr_interlocks \
  (mips_opts.isa != ISA_MIPS1  \
   || mips_cpu == CPU_R3900)

/* As with other "interlocks" this is used by hardware that has FP
   (co-processor) interlocks.  */
/* Itbl support may require additional care here.  */
#define cop_interlocks (mips_cpu == CPU_R4300                        \
			)

/* Is this a mfhi or mflo instruction?  */
#define MF_HILO_INSN(PINFO) \
          ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))

/* MIPS PIC level.  */

enum mips_pic_level
{
  /* Do not generate PIC code.  */
  NO_PIC,

  /* Generate PIC code as in Irix 4.  This is not implemented, and I'm
     not sure what it is supposed to do.  */
  IRIX4_PIC,

  /* Generate PIC code as in the SVR4 MIPS ABI.  */
  SVR4_PIC,

  /* Generate PIC code without using a global offset table: the data
     segment has a maximum size of 64K, all data references are off
     the $gp register, and all text references are PC relative.  This
     is used on some embedded systems.  */
  EMBEDDED_PIC
};

static enum mips_pic_level mips_pic;

/* 1 if we should generate 32 bit offsets from the GP register in
   SVR4_PIC mode.  Currently has no meaning in other modes.  */
static int mips_big_got;

/* 1 if trap instructions should used for overflow rather than break
   instructions.  */
static int mips_trap;

/* 1 if double width floating point constants should not be constructed
   by a assembling two single width halves into two single width floating
   point registers which just happen to alias the double width destination
   register.  On some architectures this aliasing can be disabled by a bit
   in the status register, and the setting of this bit cannot be determined
   automatically at assemble time.  */
static int mips_disable_float_construction;

/* Non-zero if any .set noreorder directives were used.  */

static int mips_any_noreorder;

/* Non-zero if nops should be inserted when the register referenced in
   an mfhi/mflo instruction is read in the next two instructions.  */
static int mips_7000_hilo_fix;

/* The size of the small data section.  */
static unsigned int g_switch_value = 8;
/* Whether the -G option was used.  */
static int g_switch_seen = 0;

#define N_RMASK 0xc4
#define N_VFP   0xd4

/* If we can determine in advance that GP optimization won't be
   possible, we can skip the relaxation stuff that tries to produce
   GP-relative references.  This makes delay slot optimization work
   better.

   This function can only provide a guess, but it seems to work for
   gcc output.  It needs to guess right for gcc, otherwise gcc
   will put what it thinks is a GP-relative instruction in a branch
   delay slot.

   I don't know if a fix is needed for the SVR4_PIC mode.  I've only
   fixed it for the non-PIC mode.  KR 95/04/07  */
static int nopic_need_relax PARAMS ((symbolS *, int));

/* handle of the OPCODE hash table */
static struct hash_control *op_hash = NULL;

/* The opcode hash table we use for the mips16.  */
static struct hash_control *mips16_op_hash = NULL;

/* This array holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful */
const char comment_chars[] = "#";

/* This array holds the chars that only start a comment at the beginning of
   a line.  If the line seems to have the form '# 123 filename'
   .line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
   first line of the input file.  This is because the compiler outputs
   #NO_APP at the beginning of its output.  */
/* Also note that C style comments are always supported.  */
const char line_comment_chars[] = "#";

/* This array holds machine specific line separator characters.  */
const char line_separator_chars[] = ";";

/* Chars that can be used to separate mant from exp in floating point nums */
const char EXP_CHARS[] = "eE";

/* Chars that mean this number is a floating point constant */
/* As in 0f12.456 */
/* or    0d1.2345e12 */
const char FLT_CHARS[] = "rRsSfFdDxXpP";

/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
   changed in read.c .  Ideally it shouldn't have to know about it at all,
   but nothing is ideal around here.
 */