m88k.h

来自「基于4个mips核的noc设计」· C头文件 代码 · 共 924 行 · 第 1/5 页

/* Table of opcodes for the motorola 88k family.
   Copyright 1989, 1990, 1991, 1993 Free Software Foundation, Inc.

This file is part of GDB and GAS.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/*
 *			Disassembler Instruction Table
 *
 *	The first field of the table is the opcode field. If an opcode
 *	is specified which has any non-opcode bits on, a system error
 *	will occur when the system attempts the install it into the
 *	instruction table.  The second parameter is a pointer to the
 *	instruction mnemonic. Each operand is specified by offset, width,
 *	and type. The offset is the bit number of the least significant
 *	bit of the operand with bit 0 being the least significant bit of
 *	the instruction. The width is the number of bits used to specify
 *	the operand. The type specifies the output format to be used for
 *	the operand. The valid formats are: register, register indirect,
 *	hex constant, and bit field specification.  The last field is a
 *	pointer to the next instruction in the linked list.  These pointers
 *	are initialized by init_disasm().
 *
 *				Structure Format
 *
 *       struct INSTAB {
 *          UPINT opcode;
 *          char *mnemonic;
 *          struct OPSPEC op1,op2,op3;
 *          struct SIM_FLAGS flgs;
 *          struct INSTAB *next;
 *       }
 *
 *       struct OPSPEC {
 *          UPINT offset:5;
 *          UPINT width:6;
 *          UPINT type:5;
 *       }
 *
 *				Revision History
 *
 *	Revision 1.0	11/08/85	Creation date
 *		 1.1	02/05/86	Updated instruction mnemonic table MD
 *		 1.2	06/16/86	Updated SIM_FLAGS for floating point
 *		 1.3	09/20/86	Updated for new encoding
 *		 	05/11/89	R. Trawick adapted from Motorola disassembler
 */

#include <stdio.h>


/*
 * This file contains the structures and constants needed to build the M88000
 * simulator.  It is the main include file, containing all the
 * structures, macros and definitions except for the floating point
 * instruction set.
 */

/*
 * The following flag informs the Simulator as to what type of byte ordering
 * will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type
 * of ordering shall be used.
*/

/* # define     BOFLAG   1 */                       /* BYTE ORDERING FLAG */

/* define the number of bits in the primary opcode field of the instruction,
 * the destination field, the source 1 and source 2 fields.
 */
# define    OP       8                        /* size of opcode field */
# define    DEST     6                        /* size of destination  */
# define    SOURCE1  6                        /* size of source1      */
# define    SOURCE2  6                        /* size of source2      */

# define    REGs    32                        /* number of registers  */

# define    WORD    long
# define    FLAG    unsigned
# define    STATE   short

# define    TRUE     1
# define    FALSE    0

# define    READ     0
# define    WRITE    1

/* The next four equates define the priorities that the various classes
 * of instructions have regarding writing results back into registers and
 * signalling exceptions.
 */
/* PMEM is also defined in <sys/param.h> on Delta 88's.  Sigh!  */
#undef PMEM

# define    PINT  0   /* Integer Priority */
# define    PFLT  1   /* Floating Point Priority */
# define    PMEM  2   /* Memory Priority */
# define    NA    3   /* Not Applicable, instruction doesnt write to regs */
# define    HIPRI 3   /* highest of these priorities */

/* The instruction registers are an artificial mechanism to speed up
 * simulator execution.  In the real processor, an instruction register
 * is 32 bits wide.  In the simulator, the 32 bit instruction is kept in
 * a structure field called rawop, and the instruction is partially decoded,
 * and split into various fields and flags which make up the other fields
 * of the structure.
 * The partial decode is done when the instructions are initially loaded
 * into simulator memory.  The simulator code memory is not an array of
 * 32 bit words, but is an array of instruction register structures.
 * Yes this wastes memory, but it executes much quicker.
 */

struct IR_FIELDS {
		    unsigned        op:OP,
				    dest: DEST,
				    src1: SOURCE1,
				    src2: SOURCE2;
			      int   ltncy,
				    extime,
				    wb_pri;     /* writeback priority     */
		    unsigned        imm_flags:2,/* immediate size         */
				    rs1_used:1, /* register source 1 used */
				    rs2_used:1, /* register source 2 used */
				    rsd_used:1, /* register source/dest. used */
				    c_flag:1,   /* complement      */
				    u_flag:1,   /* upper half word */
				    n_flag:1,   /* execute next    */
				    wb_flag:1,  /* uses writeback slot */
				    dest_64:1,  /* dest size       */
				    s1_64:1,    /* source 1 size   */
				    s2_64:1,    /* source 2 size   */
				    scale_flag:1, /* scaled register */
				    brk_flg:1;
                 };

struct	mem_segs {
	struct mem_wrd *seg;			/* pointer (returned by calloc) to segment */
	unsigned long baseaddr;			/* base load address from file headers */
	unsigned long endaddr;			/* Ending address of segment */
	int	      flags;			/* segment control flags (none defined 12/5/86) */
};

#define	MAXSEGS		(10)			/* max number of segment allowed */
#define	MEMSEGSIZE	(sizeof(struct mem_segs))/* size of mem_segs structure */


#define BRK_RD		(0x01)			/* break on memory read */
#define BRK_WR		(0x02)			/* break on memory write */
#define BRK_EXEC	(0x04)			/* break on execution */
#define	BRK_CNT		(0x08)			/* break on terminal count */


struct	mem_wrd {
	struct IR_FIELDS opcode;		/* simulator instruction break down */
	union {
		unsigned long  l;		/* memory element break down */
		unsigned short s[2];
		unsigned char  c[4];
	} mem;
};

#define	MEMWRDSIZE	(sizeof(struct mem_wrd))	/* size of each 32 bit memory model */

/* External declarations */

extern	struct mem_segs memory[];
extern	struct PROCESSOR m78000;

struct  PROCESSOR   {
	     unsigned WORD
			    ip,          /* execute instruction pointer */
			    vbr,         /* vector base register */
			    psr;         /* processor status register */