dword_reg_sel.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 35 行

module DWORD_REG_SEL(clk, disable__18, select, din, dout, dout_select);
    input clk;
    wire clk;
    input disable__18;
    wire disable__18;
    input select;
    wire select;
    input [31:0] din;
    wire [31:0] din;
    output [31:0] dout;
    reg [31:0] dout;
    output [31:0] dout_select;
    reg [31:0] dout_select;
    reg [31:0] data;
    reg [31:0] __tmp78;
    
    always @(posedge clk)
        begin : reg__19
            if (!disable__18)
                data <= din;
        end

    
    always @(select or data or din)
        begin : out
            dout = data;
            if (select)
                __tmp78 = data;
            else
                __tmp78 = din;
            dout_select = __tmp78;
        end

endmodule