mem_buffer.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 18 行

module MEM_BUFFER(din, addrin, dout, addrout);
    input [31:0] din;
    wire [31:0] din;
    input [31:0] addrin;
    wire [31:0] addrin;
    output [31:0] dout;
    reg [31:0] dout;
    output [31:0] addrout;
    reg [31:0] addrout;
    
    always @(din or addrin)
        begin : out
            dout = din;
            addrout = addrin;
        end

endmodule