add.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 21 行

module ADD(a, b, r);
    input [31:0] a;
    wire [31:0] a;
    input [31:0] b;
    wire [31:0] b;
    output [31:0] r;
    reg [31:0] r;
    reg signed [31:0] a_t;
    reg signed [31:0] b_t;
    reg signed [31:0] r_t;
    
    always @(a or b)
        begin : add_thread
            a_t = a;
            b_t = b;
            r_t = a_t + b_t;
            r = r_t;
        end

endmodule