memdev.v

基于4个mips核的noc设计

module MEMDEV(clk, a_read, a_read_reg, d_read, d_write, w, r, dmem_wait, ram_dout, ram_wait, ram_w, ram_r, ram_addr, ram_din, dev_dout, dev_rdyr, dev_rdyw, dev_w, dev_r, dev_din, dev_wdata, dev_waddr, dev_rcv_eop, dev_send_eop);
    input clk;
    wire clk;
    input [31:0] a_read;
    wire [31:0] a_read;
    input [31:0] a_read_reg;
    wire [31:0] a_read_reg;
    output [31:0] d_read;
    reg [31:0] d_read;
    input [31:0] d_write;
    wire [31:0] d_write;
    input [1:0] w;
    wire [1:0] w;
    input [1:0] r;
    wire [1:0] r;
    output dmem_wait;
    reg dmem_wait;
    input [31:0] ram_dout;
    wire [31:0] ram_dout;
    input ram_wait;
    wire ram_wait;
    output [1:0] ram_w;
    reg [1:0] ram_w;
    output [1:0] ram_r;
    reg [1:0] ram_r;
    output [31:0] ram_addr;
    reg [31:0] ram_addr;
    output [31:0] ram_din;
    reg [31:0] ram_din;
    input [31:0] dev_dout;
    wire [31:0] dev_dout;
    input dev_rdyr;
    wire dev_rdyr;
    input dev_rdyw;
    wire dev_rdyw;
    output dev_w;
    reg dev_w;
    output dev_r;
    reg dev_r;
    output [31:0] dev_din;
    reg [31:0] dev_din;
    output dev_wdata;
    reg dev_wdata;
    output dev_waddr;
    reg dev_waddr;
    input dev_rcv_eop;
    wire dev_rcv_eop;
    output dev_send_eop;
    reg dev_send_eop;
    reg [31:0] dev_buffer;
    reg bufw;
    reg sending;
    reg n_sending;
    reg dev_select;
    reg reg_dev_select;
    reg addr;
    reg addr_reg;
    reg send;
    reg eop;
    reg [1:0] __tmp61;
    reg [1:0] __tmp62;
    reg wr;
    reg rd;
    reg s;
    reg r__1;
    reg [31:0] status;
    reg [31:0] __tmp64;
    reg [31:0] __tmp63;
    
    always @(posedge clk)
        begin : buffer
            if (bufw)
                dev_buffer <= dev_dout;
            sending <= n_sending;
        end

    
    always @(a_read or a_read_reg or d_write or w or r or sending or ram_dout or ram_wait or dev_rdyw or dev_rdyr or dev_buffer or dev_rcv_eop)
        begin : memdev_process
            dev_select = a_read[5'b11111] == 1;
            reg_dev_select = a_read_reg[5'b11111] == 1;
            addr = a_read[5'b00010] == 1;
            addr_reg = a_read_reg[5'b00010] == 1;
            send = d_write[5'b10001] == 1;
            eop = d_write[5'b10100] == 1;
            ram_addr = a_read;
            ram_din = d_write;
            if (!dev_select)
                __tmp61 = w;
            else
                __tmp61 = 2'b00;
            ram_w = __tmp61;
            if (!dev_select)
                __tmp62 = r;
            else
                __tmp62 = 2'b00;
            ram_r = __tmp62;
            bufw = dev_select;
            dev_din = d_write;
            wr = dev_select && w[1'b0] != 0;
            rd = dev_select && r[1'b0] != 0;
            s = wr && send && addr;
            r__1 = rd && !addr;
            dev_w = s;
            dev_r = r__1;
            dev_send_eop = s && eop;
            dev_wdata = wr && !addr;
            dev_waddr = wr && addr;
            n_sending = s || sending && !dev_rdyw;
            status = 32'b00000000000000000000000000000000;
            status[5'b10000] = dev_rdyr;
            status[5'b10010] = !sending;
            status[5'b10011] = dev_rcv_eop;
            if (reg_dev_select)
            begin
                if (addr_reg)
                    __tmp64 = status;
                else
                    __tmp64 = dev_buffer;
                __tmp63 = __tmp64;
            end
            else
                __tmp63 = ram_dout;
            d_read = __tmp63;
            dmem_wait = !reg_dev_select && ram_wait;
        end

endmodule