reg2_sel.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 35 行

module REG2_SEL(clk, disable__20, select, din, dout, dout_select);
    input clk;
    wire clk;
    input disable__20;
    wire disable__20;
    input select;
    wire select;
    input [1:0] din;
    wire [1:0] din;
    output [1:0] dout;
    reg [1:0] dout;
    output [1:0] dout_select;
    reg [1:0] dout_select;
    reg [1:0] data;
    reg [1:0] __tmp79;
    
    always @(posedge clk)
        begin : reg__21
            if (!disable__20)
                data <= din;
        end

    
    always @(select or data or din)
        begin : out
            dout = data;
            if (select)
                __tmp79 = data;
            else
                __tmp79 = din;
            dout_select = __tmp79;
        end

endmodule