mux2.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 22 行

module MUX2(in0, in1, sel, out);
    input [31:0] in0;
    wire [31:0] in0;
    input [31:0] in1;
    wire [31:0] in1;
    input [0:0] sel;
    wire [0:0] sel;
    output [31:0] out;
    reg [31:0] out;
    reg [31:0] data;
    
    always @(in0 or in1 or sel)
        begin : mux_thread
            if (sel == 1'b0)
                data = in0;
            else
                data = in1;
            out = data;
        end

endmodule