signal_dbg.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 41 行

module SIGNAL_DBG(DO, clk, ctrl_enable, ctrl_hazard_pcwrite, ctrl_hazard_ifidwrite, ctrl_hazard_hazard, pipe_en, dmem_en, imem_en, decoder_nb_instr_20_16, decoder_nb_instr_25_21, clock, enable, reset, sig32);
    output signed  [31:0] DO;
    reg signed [31:0] DO;
    input clk;
    wire clk;
    input [0:0] ctrl_enable;
    wire [0:0] ctrl_enable;
    input [0:0] ctrl_hazard_pcwrite;
    wire [0:0] ctrl_hazard_pcwrite;
    input [0:0] ctrl_hazard_ifidwrite;
    wire [0:0] ctrl_hazard_ifidwrite;
    input [0:0] ctrl_hazard_hazard;
    wire [0:0] ctrl_hazard_hazard;
    input [0:0] pipe_en;
    wire [0:0] pipe_en;
    input [0:0] dmem_en;
    wire [0:0] dmem_en;
    input [0:0] imem_en;
    wire [0:0] imem_en;
    input [4:0] decoder_nb_instr_20_16;
    wire [4:0] decoder_nb_instr_20_16;
    input [4:0] decoder_nb_instr_25_21;
    wire [4:0] decoder_nb_instr_25_21;
    input clock;
    wire clock;
    input enable;
    wire enable;
    input reset;
    wire reset;
    input [31:0] sig32;
    wire [31:0] sig32;
    reg [0:0] one;
    
    always @(clk or ctrl_enable or ctrl_hazard_pcwrite or ctrl_hazard_ifidwrite or ctrl_hazard_hazard or pipe_en or dmem_en or imem_en or decoder_nb_instr_25_21 or decoder_nb_instr_20_16 or clock or enable or reset or sig32)
        begin : join__17
            one = 1'b1;
            DO = {one, sig32[9:0], decoder_nb_instr_25_21, decoder_nb_instr_20_16, ctrl_hazard_hazard, ctrl_hazard_pcwrite, ctrl_hazard_ifidwrite, pipe_en, dmem_en, imem_en, ctrl_enable, clk, reset, enable, clock};
        end

endmodule