ecube_router_1dim.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 75 行

module ECUBE_ROUTER_1DIM(clk, rst, addr, xin, din, xout, dout, dreq_in, dack_in, dreq_out, dack_out, x0req_in, x1req_in, x0ack_in, x1ack_in, x0req_out, x1req_out, x0ack_out, x1ack_out);
    input clk;
    wire clk;
    input rst;
    wire rst;
    input [7:0] addr;
    wire [7:0] addr;
    input [17:0] xin;
    wire [17:0] xin;
    input [17:0] din;
    wire [17:0] din;
    output [17:0] xout;
    output [17:0] dout;
    input dreq_in;
    wire dreq_in;
    input dack_in;
    wire dack_in;
    output dreq_out;
    output dack_out;
    input x0req_in;
    wire x0req_in;
    input x1req_in;
    wire x1req_in;
    input x0ack_in;
    wire x0ack_in;
    input x1ack_in;
    wire x1ack_in;
    output x0req_out;
    output x1req_out;
    output x0ack_out;
    output x1ack_out;
    wire [17:0] arb_data0;
    wire [17:0] arb_data1;
    wire arb_req0;
    wire arb_req1;
    wire arb_ack0;
    wire arb_ack1;
    wire req2out;
    wire ack2in;
    wire [17:0] data2out;
    wire req1out;
    wire ack1in;
    wire [17:0] data1out;
    wire req0out;
    wire ack0in;
    wire [17:0] data0out;
    wire [1:0] select0;
    wire [1:0] select1;
    wire [1:0] select2;
    wire rqs0;
    wire rqs1;
    wire rqs2;
    wire [17:0] data0in;
    wire [17:0] data1in;
    wire [17:0] data2in;
    wire req0in;
    wire req1in;
    wire req2in;
    wire ack0out;
    wire ack1out;
    wire ack2out;
    wire gnd;
    wire vcc;
    OUTPUT_ARBITER arbiter(.clk(clk), .rst(rst), .data0(arb_data0), .data1(arb_data1), .req0in(arb_req0), .req1in(arb_req1), .ack0out(arb_ack0), .ack1out(arb_ack1), .data(xout), .req0out(x0req_out), .req1out(x1req_out), .ack0in(x0ack_in), .ack1in(x1ack_in));
    OUTPUT_QUEUE dqueue(.clk(clk), .rst(rst), .ack(dack_in), .req(dreq_out), .data(dout), .req_in(req2out), .ack_in(ack2in), .data_in(data2out));
    OUTPUT_QUEUE x1queue(.clk(clk), .rst(rst), .ack(arb_ack1), .req(arb_req1), .data(arb_data1), .req_in(req1out), .ack_in(ack1in), .data_in(data1out));
    OUTPUT_QUEUE x0queue(.clk(clk), .rst(rst), .ack(arb_ack0), .req(arb_req0), .data(arb_data0), .req_in(req0out), .ack_in(ack0in), .data_in(data0out));
    CROSSBAR3x3 swtch(.clk(clk), .addr_0(select0), .addr_1(select1), .addr_2(select2), .conn_0(rqs0), .conn_1(rqs1), .conn_2(rqs2), .data_in_0(data0in), .data_in_1(data1in), .data_in_2(data2in), .req_in_0(req0in), .req_in_1(req1in), .req_in_2(req2in), .ack_in_0(ack0in), .ack_in_1(ack1in), .ack_in_2(ack2in), .data_out_0(data0out), .data_out_1(data1out), .data_out_2(data2out), .req_out_0(req0out), .req_out_1(req1out), .req_out_2(req2out), .ack_out_0(ack0out), .ack_out_1(ack1out), .ack_out_2(ack2out));
    INPUT_CTRL dinctrl(.clk(clk), .rst(rst), .my_address(addr), .ch0(gnd), .ch1(gnd), .req(dreq_in), .ack(dack_out), .data(din), .out_select(select2), .request_switch(rqs2), .data_out(data2in), .out_req(req2in), .out_ack(ack2out));
    INPUT_CTRL x1inctrl(.clk(clk), .rst(rst), .my_address(addr), .ch0(gnd), .ch1(vcc), .req(x1req_in), .ack(x1ack_out), .data(xin), .out_select(select1), .request_switch(rqs1), .data_out(data1in), .out_req(req1in), .out_ack(ack1out));
    INPUT_CTRL x0inctrl(.clk(clk), .rst(rst), .my_address(addr), .ch0(vcc), .ch1(gnd), .req(x0req_in), .ack(x0ack_out), .data(xin), .out_select(select0), .request_switch(rqs0), .data_out(data0in), .out_req(req0in), .out_ack(ack0out));
    assign gnd = 0;
    assign vcc = 1;
endmodule