signextend_byte.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 22 行

module SIGNEXTEND_BYTE(in, out);
    input [31:0] in;
    wire [31:0] in;
    output [31:0] out;
    reg [31:0] out;
    reg [31:0] a;
    reg [31:0] b;
    reg signed [6:0] i__loop_59;
    reg signed [31:0] i;
    
    always @(in)
        begin : signextend_thread
            a = in;
            b[7:0] = a[31:24];
            for (i__loop_59 = 7'sb0001000 ; i__loop_59 < 7'sb0100000 ; i__loop_59 = 7'sb0000001 + i__loop_59)
                        b[i__loop_59] = a[5'b11111];
            i = i__loop_59;
            out = b;
        end

endmodule