xram.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 42 行

module XRAM(DO, ADDR, DI, CLK, WE);
    output signed  [31:0] DO;
    input [31:0] ADDR;
    wire [31:0] ADDR;
    input signed  [31:0] DI;
    wire signed [31:0] DI;
    input CLK;
    wire CLK;
    input WE;
    wire WE;
    wire wCLK;
    wire [10:0] addr_cnt;
    wire signed [7:0] DO0;
    wire signed [7:0] DO1;
    wire signed [7:0] DO2;
    wire signed [7:0] DO3;
    wire signed [7:0] DI0;
    wire signed [7:0] DI1;
    wire signed [7:0] DI2;
    wire signed [7:0] DI3;
    wire [10:0] wADDR;
    wire [10:0] rADDR;
    wire signed [7:0] out;
    wire signed [0:0] pout;
    wire signed [0:0] zero1;
    wire one;
    wire zero;
    wire signed [7:0] zero8;
    wire [10:0] zero11;
    XRAM_CNT cnt(.clk(wCLK), .en(WE), .cnt(addr_cnt));
    XRAMCONV conv(.DO(DO), .ADDR(ADDR), .DI(DI), .CLK(CLK), .addr_cnt(addr_cnt), .DO0(DO0), .DO1(DO1), .DO2(DO2), .DO3(DO3), .DI0(DI0), .DI1(DI1), .DI2(DI2), .DI3(DI3), .wADDR(wADDR), .rADDR(rADDR), .wCLK(wCLK));
    RAMB16_S9_S9 bram3(.DOA(out), .DOPA(pout), .ADDRA(wADDR), .DIA(DI3), .DIPA(zero1), .ENA(one), .CLKA(wCLK), .WEA(WE), .SSRA(zero), .DOB(DO3), .DOPB(pout), .ADDRB(rADDR), .DIB(zero8), .DIPB(zero1), .ENB(one), .CLKB(CLK), .WEB(zero), .SSRB(zero));
    RAMB16_S9_S9 bram2(.DOA(out), .DOPA(pout), .ADDRA(wADDR), .DIA(DI2), .DIPA(zero1), .ENA(one), .CLKA(wCLK), .WEA(WE), .SSRA(zero), .DOB(DO2), .DOPB(pout), .ADDRB(rADDR), .DIB(zero8), .DIPB(zero1), .ENB(one), .CLKB(CLK), .WEB(zero), .SSRB(zero));
    RAMB16_S9_S9 bram1(.DOA(out), .DOPA(pout), .ADDRA(wADDR), .DIA(DI1), .DIPA(zero1), .ENA(one), .CLKA(wCLK), .WEA(WE), .SSRA(zero), .DOB(DO1), .DOPB(pout), .ADDRB(rADDR), .DIB(zero8), .DIPB(zero1), .ENB(one), .CLKB(CLK), .WEB(zero), .SSRB(zero));
    RAMB16_S9_S9 bram0(.DOA(out), .DOPA(pout), .ADDRA(wADDR), .DIA(DI0), .DIPA(zero1), .ENA(one), .CLKA(wCLK), .WEA(WE), .SSRA(zero), .DOB(DO0), .DOPB(pout), .ADDRB(rADDR), .DIB(zero8), .DIPB(zero1), .ENB(one), .CLKB(CLK), .WEB(zero), .SSRB(zero));
    assign one = 1;
    assign zero = 0;
    assign zero1 = 1'sb0;
    assign zero11 = 11'b00000000000;
    assign zero8 = 8'sb00000000;
endmodule