brom16k_wrapper.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 106 行

module BROM16K_WRAPPER(addr, dout, en, clk, memwait, ADDR, DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07, EN, CLK, SSR, WE, DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07);
    input [31:0] addr;
    wire [31:0] addr;
    output [31:0] dout;
    reg [31:0] dout;
    input [0:0] en;
    wire [0:0] en;
    input clk;
    wire clk;
    output memwait;
    reg memwait;
    output [11:0] ADDR;
    reg [11:0] ADDR;
    output signed  [3:0] DI00;
    reg signed [3:0] DI00;
    output signed  [3:0] DI01;
    reg signed [3:0] DI01;
    output signed  [3:0] DI02;
    reg signed [3:0] DI02;
    output signed  [3:0] DI03;
    reg signed [3:0] DI03;
    output signed  [3:0] DI04;
    reg signed [3:0] DI04;
    output signed  [3:0] DI05;
    reg signed [3:0] DI05;
    output signed  [3:0] DI06;
    reg signed [3:0] DI06;
    output signed  [3:0] DI07;
    reg signed [3:0] DI07;
    output EN;
    reg EN;
    output CLK;
    reg CLK;
    output SSR;
    reg SSR;
    output WE;
    reg WE;
    input signed  [3:0] DO00;
    wire signed [3:0] DO00;
    input signed  [3:0] DO01;
    wire signed [3:0] DO01;
    input signed  [3:0] DO02;
    wire signed [3:0] DO02;
    input signed  [3:0] DO03;
    wire signed [3:0] DO03;
    input signed  [3:0] DO04;
    wire signed [3:0] DO04;
    input signed  [3:0] DO05;
    wire signed [3:0] DO05;
    input signed  [3:0] DO06;
    wire signed [3:0] DO06;
    input signed  [3:0] DO07;
    wire signed [3:0] DO07;
    reg [31:0] a;
    reg [11:0] a_13_2;
    reg [11:0] addr12;
    reg e;
    reg [3:0] d0;
    reg [3:0] d1;
    reg [3:0] d2;
    reg [3:0] d3;
    reg [3:0] d4;
    reg [3:0] d5;
    reg [3:0] d6;
    reg [3:0] d7;
    reg [31:0] data32;
    
    always @(addr or en or clk)
        begin : in
            a = addr;
            a_13_2 = a[13:2];
            addr12 = a_13_2;
            ADDR = addr12;
            DI00 = 4'sb0000;
            DI01 = 4'sb0000;
            DI02 = 4'sb0000;
            DI03 = 4'sb0000;
            DI04 = 4'sb0000;
            DI05 = 4'sb0000;
            DI06 = 4'sb0000;
            DI07 = 4'sb0000;
            e = en[1'b0] != 0;
            EN = e;
            WE = 0;
            SSR = 0;
            CLK = clk;
        end

    
    always @(DO00 or DO01 or DO02 or DO03 or DO04 or DO05 or DO06 or DO07)
        begin : out
            d0 = DO00;
            d1 = DO01;
            d2 = DO02;
            d3 = DO03;
            d4 = DO04;
            d5 = DO05;
            d6 = DO06;
            d7 = DO07;
            data32 = {d0, d1, d2, d3, d4, d5, d6, d7};
            dout = data32;
            memwait = 0;
        end

endmodule