network_interface.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 313 行

module NETWORK_INTERFACE(clk, rst, reg_data_in, write_data, write_addr, send, packet_end, read, reg_data_out, data_rdy, rcv_packet_end, send_rdy, data_in, req_in, ack_in, data_out, req_out, ack_out);
    input clk;
    wire clk;
    input rst;
    wire rst;
    input [31:0] reg_data_in;
    wire [31:0] reg_data_in;
    input write_data;
    wire write_data;
    input write_addr;
    wire write_addr;
    input send;
    wire send;
    input packet_end;
    wire packet_end;
    input read;
    wire read;
    output [31:0] reg_data_out;
    reg [31:0] reg_data_out;
    output data_rdy;
    reg data_rdy;
    output rcv_packet_end;
    reg rcv_packet_end;
    output send_rdy;
    reg send_rdy;
    input [17:0] data_in;
    wire [17:0] data_in;
    input req_in;
    wire req_in;
    input ack_in;
    wire ack_in;
    output [17:0] data_out;
    reg [17:0] data_out;
    output req_out;
    reg req_out;
    output ack_out;
    reg ack_out;
    reg [31:0] buffer_in;
    reg [31:0] buffer_out;
    reg [15:0] addr;
    reg [15:0] buffer_addr;
    reg packet_end_reg;
    reg wr_packet_end;
    reg [1:0] flit_type_v;
    reg [7:0] addrx;
    reg [7:0] addry;
    reg [15:0] flit_data_v;
    reg [1:0] next_send_flit;
    reg [1:0] send_flit;
    reg [2:0] send_next_state;
    reg req_out_v;
    reg send_rdy_v;
    reg wr_packet_end_v;
    reg [1:0] __tmp69;
    reg [2:0] send_current_state;
    reg [1:0] flit_type__1;
    reg [1:0] rcv_next_state;
    reg [1:0] next_rcv_flit;
    reg [1:0] rcv_flit;
    reg [31:0] buffer_in_n;
    reg ack_out_v;
    reg data_rdy_v;
    reg rcv_packet_end_v;
    reg [1:0] rcv_current_state;
    
    always @(buffer_in)
        begin : forward_buffer
            reg_data_out = buffer_in;
        end

    
    always @(posedge clk or posedge rst)
        begin : buffer_out_process
            if (rst)
                buffer_out <= 32'b00000000000000000000000000000000;
            else
            begin
                if (write_data)
                    buffer_out <= reg_data_in;
            end
        end

    
    always @(posedge clk or posedge rst)
        begin : buffer_addr_process
            if (rst)
            begin
                addr = reg_data_in[15:0];
                buffer_addr <= 16'b0000000000000000;
            end
            else
            begin
                addr = reg_data_in[15:0];
                if (write_addr)
                    buffer_addr <= addr;
            end
        end

    
    always @(posedge clk or posedge rst)
        begin : register_packet_end
            if (rst)
                packet_end_reg <= 0;
            else
            begin
                if (wr_packet_end)
                    packet_end_reg <= packet_end;
            end
        end

    
    always @(send_current_state or send_flit or send or buffer_out or buffer_addr or ack_in or packet_end_reg)
        begin : send_logic
            flit_type_v = 2'b00;
            addrx = buffer_addr[15:8];
            addry = buffer_addr[7:0];
            flit_data_v = 16'b0000000000000000;
            next_send_flit = send_flit;
            send_next_state = 3'b000;
            req_out_v = 0;
            send_rdy_v = 0;
            wr_packet_end_v = 0;
            case (send_current_state) //synopsys parallel_case full_case
            0:              if (send)
            begin
                send_next_state = 3'b001;
                next_send_flit = 2'b01;
                wr_packet_end_v = 1;
            end
            else
            begin
                send_next_state = 3'b000;
                next_send_flit = 2'b00;
                send_rdy_v = 1;
            end
            1:  begin
                req_out_v = 1;
                case (send_flit) //synopsys parallel_case
                1:  begin
                    flit_type_v = 2'b01;
                    flit_data_v = {addrx, addry};
                end
                2:  begin
                    flit_type_v = 2'b00;
                    flit_data_v = buffer_out[31:16];
                end
                3:  begin
                    if (packet_end_reg)
                        __tmp69 = 2'b10;
                    else
                        __tmp69 = 2'b00;
                    flit_type_v = __tmp69;
                    flit_data_v = buffer_out[15:0];
                end
                default : begin 
                    end
                endcase
                if (ack_in)
                    send_next_state = 3'b010;
                else
                    send_next_state = 3'b001;
            end
            2:              if (!ack_in)
                case (send_flit) //synopsys parallel_case
                1:  begin
                    send_next_state = 3'b001;
                    next_send_flit = 2'b10;
                end
                2:  begin
                    send_next_state = 3'b001;
                    next_send_flit = 2'b11;
                end
                3:  begin
                    send_next_state = 3'b011;
                    next_send_flit = 2'b00;
                    send_rdy_v = 1;
                end
                default : begin 
                    end
                endcase
            else
                send_next_state = 3'b010;
            3:  begin
                send_rdy_v = 1;
                if (!send)
                begin
                    if (packet_end_reg)
                        send_next_state = 3'b000;
                    else
                        send_next_state = 3'b100;
                end
                else
                    send_next_state = 3'b011;
            end
            4:  begin
                next_send_flit = 2'b10;
                if (send)
                begin
                    send_next_state = 3'b001;
                    wr_packet_end_v = 1;
                end
                else
                begin
                    send_next_state = 3'b100;
                    send_rdy_v = 1;
                end
            end
            endcase
            wr_packet_end = wr_packet_end_v;
            req_out = req_out_v;
            send_rdy = send_rdy_v;
            data_out = {flit_type_v, flit_data_v};
        end

    
    always @(posedge clk or posedge rst)
        begin : send_change_state
            if (rst)
            begin
                send_current_state <= 3'b000;
                send_flit <= 2'b00;
            end
            else
            begin
                send_current_state <= send_next_state;
                send_flit <= next_send_flit;
            end
        end

    
    always @(rcv_current_state or rcv_flit or req_in or data_in or buffer_in or read)
        begin : rcv_logic
            flit_type__1 = data_in[17:16];
            rcv_next_state = 2'b00;
            next_rcv_flit = rcv_flit;
            buffer_in_n = buffer_in;
            ack_out_v = 0;
            data_rdy_v = 0;
            rcv_packet_end_v = 0;
            case (rcv_current_state) //synopsys parallel_case full_case
            0:              if (req_in)
            begin
                rcv_next_state = 2'b01;
                case (rcv_flit) //synopsys parallel_case full_case
                0:  begin
                    buffer_in_n = 32'b00000000000000000000000000000000;
                    next_rcv_flit = 2'b01;
                end
                1:                  buffer_in_n = 32'b00000000000000000000000000000000;
                2:                  buffer_in_n = {data_in[15:0], buffer_in[15:0]};
                3:                  buffer_in_n = {buffer_in[31:16], data_in[15:0]};
                endcase
            end
            else
                rcv_next_state = 2'b00;
            1:  begin
                ack_out_v = 1;
                if (!req_in)
                    case (rcv_flit) //synopsys parallel_case
                    1:  begin
                        rcv_next_state = 2'b00;
                        next_rcv_flit = 2'b10;
                    end
                    2:  begin
                        rcv_next_state = 2'b00;
                        next_rcv_flit = 2'b11;
                    end
                    3:  begin
                        rcv_next_state = 2'b10;
                        if (flit_type__1 == 2'b10)
                            next_rcv_flit = 2'b00;
                        else
                            next_rcv_flit = 2'b10;
                    end
                    default : begin 
                        end
                    endcase
                else
                    rcv_next_state = 2'b01;
            end
            2:  begin
                data_rdy_v = 1;
                rcv_packet_end_v = rcv_flit == 2'b00;
                if (read)
                    rcv_next_state = 2'b00;
                else
                    rcv_next_state = 2'b10;
            end
            endcase
            ack_out = ack_out_v;
            data_rdy = data_rdy_v;
            rcv_packet_end = rcv_packet_end_v;
        end

    
    always @(posedge clk or posedge rst)
        begin : rcv_change_state
            if (rst)
            begin
                rcv_current_state <= 2'b00;
                rcv_flit <= 2'b00;
                buffer_in <= 32'b00000000000000000000000000000000;
            end
            else
            begin
                rcv_current_state <= rcv_next_state;
                rcv_flit <= next_rcv_flit;
                buffer_in <= buffer_in_n;
            end
        end

endmodule