cache_bram_wrap.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 208 行

module CACHE_BRAM_WRAP(clk, din, valid_in, tagi, index, offset, we, en, dout, tago, valid, DOA0, DOB0, DOA1, DOB1, DOPA0, DOPB0, DOPA1, DOPB1, ADDRA0, ADDRB0, ADDRA1, ADDRB1, DIA0, DIB0, DIA1, DIB1, DIPA0, DIPB0, DIPA1, DIPB1, ENA0, ENB0, ENA1, ENB1, CLKA0, CLKB0, CLKA1, CLKB1, WEA0, WEB0, WEA1, WEB1, SSRA0, SSRB0, SSRA1, SSRB1);
    input clk;
    wire clk;
    input [31:0] din;
    wire [31:0] din;
    input valid_in;
    wire valid_in;
    input [19:0] tagi;
    wire [19:0] tagi;
    input [7:0] index;
    wire [7:0] index;
    input [1:0] offset;
    wire [1:0] offset;
    input we;
    wire we;
    input en;
    wire en;
    output [31:0] dout;
    reg [31:0] dout;
    output [19:0] tago;
    reg [19:0] tago;
    output valid;
    reg valid;
    input signed  [31:0] DOA0;
    wire signed [31:0] DOA0;
    input signed  [31:0] DOB0;
    wire signed [31:0] DOB0;
    input signed  [31:0] DOA1;
    wire signed [31:0] DOA1;
    input signed  [31:0] DOB1;
    wire signed [31:0] DOB1;
    input signed  [3:0] DOPA0;
    wire signed [3:0] DOPA0;
    input signed  [3:0] DOPB0;
    wire signed [3:0] DOPB0;
    input signed  [3:0] DOPA1;
    wire signed [3:0] DOPA1;
    input signed  [3:0] DOPB1;
    wire signed [3:0] DOPB1;
    output [8:0] ADDRA0;
    reg [8:0] ADDRA0;
    output [8:0] ADDRB0;
    reg [8:0] ADDRB0;
    output [8:0] ADDRA1;
    reg [8:0] ADDRA1;
    output [8:0] ADDRB1;
    reg [8:0] ADDRB1;
    output signed  [31:0] DIA0;
    reg signed [31:0] DIA0;
    output signed  [31:0] DIB0;
    reg signed [31:0] DIB0;
    output signed  [31:0] DIA1;
    reg signed [31:0] DIA1;
    output signed  [31:0] DIB1;
    reg signed [31:0] DIB1;
    output signed  [3:0] DIPA0;
    reg signed [3:0] DIPA0;
    output signed  [3:0] DIPB0;
    reg signed [3:0] DIPB0;
    output signed  [3:0] DIPA1;
    reg signed [3:0] DIPA1;
    output signed  [3:0] DIPB1;
    reg signed [3:0] DIPB1;
    output ENA0;
    reg ENA0;
    output ENB0;
    reg ENB0;
    output ENA1;
    reg ENA1;
    output ENB1;
    reg ENB1;
    output CLKA0;
    reg CLKA0;
    output CLKB0;
    reg CLKB0;
    output CLKA1;
    reg CLKA1;
    output CLKB1;
    reg CLKB1;
    output WEA0;
    reg WEA0;
    output WEB0;
    reg WEB0;
    output WEA1;
    reg WEA1;
    output WEB1;
    reg WEB1;
    output SSRA0;
    reg SSRA0;
    output SSRB0;
    reg SSRB0;
    output SSRA1;
    reg SSRA1;
    output SSRB1;
    reg SSRB1;
    reg [1:0] word;
    reg clk_v;
    reg en_v;
    reg we_v;
    reg [1:0] off;
    reg signed [31:0] din_v;
    reg [19:0] tag_in_v;
    reg [7:0] ix;
    reg [0:0] zero;
    reg [0:0] one;
    reg [8:0] addr0;
    reg [8:0] addr1;
    reg [3:0] tag3;
    reg [3:0] tag2;
    reg [3:0] tag1;
    reg [3:0] tag0;
    reg [4:0] zerofill;
    reg [31:0] data;
    reg vld;
    reg [2:0] t3;
    reg [3:0] t2;
    reg [3:0] t1;
    reg [3:0] t0;
    reg [19:0] tag;
    
    always @(posedge clk)
        begin : reg__17
            if (en)
                word <= offset;
        end

    
    always @(clk or din or valid_in or tagi or index or offset or we or en)
        begin : in
            clk_v = clk;
            en_v = en;
            we_v = we;
            off = offset;
            din_v = din;
            tag_in_v = tagi;
            ix = index;
            zero = 1'b0;
            one = 1'b1;
            addr0 = {ix, zero};
            addr1 = {ix, one};
            ADDRA0 = addr0;
            ADDRB0 = addr1;
            ADDRA1 = addr0;
            ADDRB1 = addr1;
            DIA0 = din_v;
            DIB0 = din_v;
            DIA1 = din_v;
            DIB1 = din_v;
            WEA0 = 0;
            WEB0 = 0;
            WEA1 = 0;
            WEB1 = 0;
            case (off) //synopsys parallel_case
            1:              WEB0 = we_v;
            2:              WEA1 = we_v;
            3:              WEB1 = we_v;
            default : begin 
                WEA0 = we_v;
                end
            endcase
            tag3[2'b11] = valid_in;
            tag3[2:0] = tag_in_v[14:12];
            tag2 = tag_in_v[11:8];
            tag1 = tag_in_v[7:4];
            tag0 = tag_in_v[3:0];
            DIPB1 = tag3;
            DIPA1 = tag2;
            DIPB0 = tag1;
            DIPA0 = tag0;
            ENA0 = en_v;
            ENB0 = en_v;
            ENA1 = en_v;
            ENB1 = en_v;
            CLKA0 = clk_v;
            CLKB0 = clk_v;
            CLKA1 = clk_v;
            CLKB1 = clk_v;
            SSRA0 = 0;
            SSRB0 = 0;
            SSRA1 = 0;
            SSRB1 = 0;
        end

    
    always @(word or DOA0 or DOPA0 or DOB0 or DOPB0 or DOA1 or DOPA1 or DOB1 or DOPB1)
        begin : out
            zerofill = 5'b00000;
            case (word) //synopsys parallel_case
            1:              data = DOB0;
            2:              data = DOA1;
            3:              data = DOB1;
            default : begin 
                data = DOA0;
                end
            endcase
            vld = DOPB1[2'b11] != 0;
            t3 = DOPB1[2:0];
            t2 = DOPA1;
            t1 = DOPB0;
            t0 = DOPA0;
            tag = {zerofill, t3, t2, t1, t0};
            dout = data;
            valid = vld;
            tago = tag;
        end

endmodule