cache_miss_ctrl.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 299 行

module CACHE_MISS_CTRL(clk, en, cache_valid, cache_tag, addr_tag, cache_en, cache_we, w, r, miss_wait, rewrite, byte_rpl, current_reg, mem_ww, mem_wb, mem_r, mem_rdy, din, addr, mem_din, mem_addr, fetch_word, fetch_word_rdy);
    input clk;
    wire clk;
    input [0:0] en;
    wire [0:0] en;
    input cache_valid;
    wire cache_valid;
    input [19:0] cache_tag;
    wire [19:0] cache_tag;
    input [19:0] addr_tag;
    wire [19:0] addr_tag;
    output cache_en;
    reg cache_en;
    output cache_we;
    reg cache_we;
    input [1:0] w;
    wire [1:0] w;
    input [1:0] r;
    wire [1:0] r;
    output miss_wait;
    reg miss_wait;
    output rewrite;
    reg rewrite;
    output byte_rpl;
    reg byte_rpl;
    output current_reg;
    reg current_reg;
    output mem_ww;
    reg mem_ww;
    output mem_wb;
    reg mem_wb;
    output mem_r;
    reg mem_r;
    input mem_rdy;
    wire mem_rdy;
    input [31:0] din;
    wire [31:0] din;
    input [31:0] addr;
    wire [31:0] addr;
    output [31:0] mem_din;
    reg [31:0] mem_din;
    output [31:0] mem_addr;
    reg [31:0] mem_addr;
    output [1:0] fetch_word;
    reg [1:0] fetch_word;
    output fetch_word_rdy;
    reg fetch_word_rdy;
    reg [31:0] current_state;
    reg [31:0] next_state;
    reg [31:0] operation;
    reg [31:0] n_operation;
    reg waiting;
    reg [1:0] next_fetch_word;
    reg word_clr;
    reg word_inc;
    reg write_in_progress;
    reg start_write;
    reg miss;
    reg [1:0] zero;
    reg en_v;
    reg [1:0] wrd;
    reg [31:0] addr_v;
    reg [1:0] r_v;
    reg [1:0] w_v;
    
    always @(posedge clk)
        begin : change_state
            current_state <= next_state;
            operation <= n_operation;
            waiting <= miss_wait;
        end

    
    always @(posedge clk)
        begin : fetch_word_reg
            if (word_clr)
            begin
                fetch_word <= next_fetch_word;
                next_fetch_word <= 2'b00;
            end
            else
            begin
                if (word_inc)
                begin
                    fetch_word <= next_fetch_word;
                    next_fetch_word <= 2'b01 + next_fetch_word;
                end
            end
        end

    
    always @(posedge clk)
        begin : write_progress
            if (start_write)
                write_in_progress <= 1;
            else
            begin
                if (mem_rdy)
                    write_in_progress <= 0;
            end
        end

    
    always @(cache_valid or cache_tag or addr_tag)
        begin : miss_detect
            miss = !cache_valid || cache_tag != addr_tag;
        end

    
    always @(current_state or operation or waiting or write_in_progress or next_fetch_word or miss or mem_rdy or din or addr or r or w or en)
        begin : logic
            zero = 2'b00;
            en_v = en[1'b0] == 1;
            miss_wait = 0;
            cache_we = 0;
            cache_en = 0;
            rewrite = 0;
            byte_rpl = 0;
            current_reg = 0;
            mem_r = 0;
            mem_ww = 0;
            mem_wb = 0;
            mem_din = din;
            wrd = next_fetch_word;
            addr_v = {addr[31:4], wrd, zero};
            mem_addr = addr;
            fetch_word_rdy = 0;
            word_inc = 0;
            word_clr = 0;
            start_write = 0;
            n_operation = operation;
            next_state = current_state;
            case (current_state) //synopsys parallel_case
            0:              if (operation != 32'b00000000000000000000000000000000 && miss && operation != 32'b00000000000000000000000000000011 && !waiting)
            begin
                if (operation == 32'b00000000000000000000000000000001)
                begin
                    if (write_in_progress && !mem_rdy)
                        next_state = 32'b00000000000000000000000000000011;
                    else
                    begin
                        next_state = 32'b00000000000000000000000000000001;
                        word_inc = 1;
                        mem_r = 1;
                        mem_addr = addr_v;
                    end
                    current_reg = 1;
                    miss_wait = 1;
                end
                else
                begin
                    miss_wait = 1;
                    rewrite = 1;
                    cache_we = 1;
                    cache_en = 1;
                    next_state = 32'b00000000000000000000000000000000;
                    n_operation = 32'b00000000000000000000000000000000;
                    current_reg = 1;
                end
            end
            else
            begin
                if (operation == 32'b00000000000000000000000000000011 && !miss && !waiting)
                begin
                    miss_wait = 1;
                    byte_rpl = 1;
                    rewrite = 1;
                    cache_we = 1;
                    cache_en = 1;
                    current_reg = 1;
                    next_state = 32'b00000000000000000000000000000000;
                    n_operation = 32'b00000000000000000000000000000000;
                end
                else
                begin
                    if (en_v)
                    begin
                        r_v = r;
                        w_v = w;
                        cache_we = w_v == 2'b01;
                        cache_en = r_v != 2'b00 || w_v != 2'b00;
                        if (w_v != 2'b00)
                        begin
                            next_state = 32'b00000000000000000000000000000000;
                            if (w_v == 2'b10)
                            begin
                                cache_en = 1;
                                mem_wb = 1;
                                start_write = 1;
                                n_operation = 32'b00000000000000000000000000000011;
                            end
                            else
                            begin
                                cache_we = 1;
                                cache_en = 1;
                                start_write = 1;
                                mem_ww = 1;
                                n_operation = 32'b00000000000000000000000000000010;
                            end
                            if (write_in_progress && !mem_rdy)
                            begin
                                start_write = 0;
                                miss_wait = 1;
                                cache_we = 0;
                                cache_en = 0;
                                mem_wb = 0;
                                mem_ww = 0;
                                next_state = 32'b00000000000000000000000000000100;
                            end
                        end
                        else
                        begin
                            if (r_v != 2'b00)
                            begin
                                n_operation = 32'b00000000000000000000000000000001;
                                next_state = 32'b00000000000000000000000000000000;
                            end
                            else
                            begin
                                n_operation = 32'b00000000000000000000000000000000;
                                next_state = 32'b00000000000000000000000000000000;
                            end
                        end
                    end
                    else
                    begin
                        next_state = 32'b00000000000000000000000000000000;
                        n_operation = operation;
                        current_reg = 1;
                    end
                end
            end
            1:  begin
                miss_wait = 1;
                current_reg = 1;
                mem_addr = addr_v;
                if (mem_rdy)
                begin
                    fetch_word_rdy = 1;
                    cache_we = 1;
                    cache_en = 1;
                    if (next_fetch_word == 2'b00)
                        next_state = 32'b00000000000000000000000000000010;
                    else
                    begin
                        word_inc = 1;
                        mem_r = 1;
                        next_state = 32'b00000000000000000000000000000001;
                    end
                end
                else
                    next_state = 32'b00000000000000000000000000000001;
            end
            2:  begin
                miss_wait = 1;
                current_reg = 1;
                cache_en = 1;
                n_operation = 32'b00000000000000000000000000000000;
                next_state = 32'b00000000000000000000000000000000;
            end
            3:  begin
                miss_wait = 1;
                if (write_in_progress)
                    next_state = 32'b00000000000000000000000000000011;
                else
                begin
                    next_state = 32'b00000000000000000000000000000001;
                    current_reg = 1;
                    word_inc = 1;
                    mem_r = 1;
                    mem_addr = addr_v;
                end
            end
            4:  begin
                miss_wait = 1;
                if (!mem_rdy)
                    next_state = 32'b00000000000000000000000000000100;
                else
                begin
                    next_state = 32'b00000000000000000000000000000000;
                    start_write = 1;
                    miss_wait = 0;
                    cache_en = 1;
                    if (operation == 32'b00000000000000000000000000000011)
                        mem_wb = 1;
                    else
                    begin
                        mem_ww = 1;
                        cache_we = 1;
                    end
                end
            end
            default : begin 
                end
            endcase
        end

endmodule