netmmips.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 57 行

module NETmMIPS(clock, enable, reset, data_in, req_in, ack_in, data_out, req_out, ack_out, bus_pc, ramDO, ramADDR, ramDI, ramEN, ramCLK, ramWE, ramRST, romDO, romADDR, romDI, romEN, romCLK, romWE, romRST);
    input clock;
    wire clock;
    input enable;
    wire enable;
    input reset;
    wire reset;
    input [17:0] data_in;
    wire [17:0] data_in;
    input req_in;
    wire req_in;
    input ack_in;
    wire ack_in;
    output [17:0] data_out;
    output req_out;
    output ack_out;
    output [31:0] bus_pc;
    output signed  [31:0] ramDO;
    input [31:0] ramADDR;
    wire [31:0] ramADDR;
    input signed  [31:0] ramDI;
    wire signed [31:0] ramDI;
    input ramEN;
    wire ramEN;
    input ramCLK;
    wire ramCLK;
    input ramWE;
    wire ramWE;
    input ramRST;
    wire ramRST;
    output signed  [31:0] romDO;
    input [31:0] romADDR;
    wire [31:0] romADDR;
    input signed  [31:0] romDI;
    wire signed [31:0] romDI;
    input romEN;
    wire romEN;
    input romCLK;
    wire romCLK;
    input romWE;
    wire romWE;
    input romRST;
    wire romRST;
    wire [31:0] dout;
    wire wdata;
    wire waddr;
    wire w;
    wire send_eop;
    wire r;
    wire [31:0] din;
    wire rdyr;
    wire rcv_eop;
    wire rdyw;
    NETWORK_INTERFACE netif(.clk(clock), .rst(reset), .reg_data_in(dout), .write_data(wdata), .write_addr(waddr), .send(w), .packet_end(send_eop), .read(r), .reg_data_out(din), .data_rdy(rdyr), .rcv_packet_end(rcv_eop), .send_rdy(rdyw), .data_in(data_in), .req_in(req_in), .ack_in(ack_in), .data_out(data_out), .req_out(req_out), .ack_out(ack_out));
    mMIPS mips(.clock(clock), .enable(enable), .reset(reset), .bus_pc(bus_pc), .romDO(romDO), .romADDR(romADDR), .romDI(romDI), .romEN(romEN), .romCLK(romCLK), .romWE(romWE), .romRST(romRST), .ramDO(ramDO), .ramADDR(ramADDR), .ramDI(ramDI), .ramEN(ramEN), .ramCLK(ramCLK), .ramWE(ramWE), .ramRST(ramRST), .dev_dout(dout), .dev_din(din), .dev_r(r), .dev_w(w), .dev_rdyr(rdyr), .dev_rdyw(rdyw), .dev_wdata(wdata), .dev_waddr(waddr), .dev_send_eop(send_eop), .dev_rcv_eop(rcv_eop));
endmodule