alu.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 83 行

module ALU(ctrl, a, b, r, z);
    input [5:0] ctrl;
    wire [5:0] ctrl;
    input [31:0] a;
    wire [31:0] a;
    input [31:0] b;
    wire [31:0] b;
    output [31:0] r;
    reg [31:0] r;
    output [0:0] z;
    reg [0:0] z;
    reg [1:0] sign2;
    reg [7:0] sign8;
    reg [31:0] s;
    reg [31:0] t;
    reg [5:0] ctrl_t;
    reg [31:0] result;
    reg [0:0] sign;
    reg signed [4:0] i__loop_125;
    reg signed [31:0] i;
    reg [0:0] zero;
    
    always @(ctrl or a or b)
        begin : alu_thread
            sign2 = 2'b00;
            sign8 = 8'b00000000;
            s = a;
            t = b;
            ctrl_t = ctrl;
            result = 32'b00000000000000000000000000000000;
            case (ctrl_t) //synopsys parallel_case
            0:              result = s & t;
            1:              result = s | t;
            2:              result = s + t;
            3:              result = s + t;
            4:              result = s ^ t;
            6:              result = s - t;
            7:              if (s < t)
                result = 32'b00000000000000000000000000000001;
            else
                result = 32'b00000000000000000000000000000000;
            8:              if (s < t)
                result = 32'b00000000000000000000000000000001;
            else
                result = 32'b00000000000000000000000000000000;
            9:              result = (t << 16);
            10:              result = (t << 1);
            11:              result = (t << 2);
            12:              result = (t << 8);
            13:              result = (t >> 1);
            14:              result = (t >> 2);
            15:              result = (t >> 8);
            16:  begin
                sign = t[31:31];
                result = (t >> 1);
                result[31:31] = sign;
            end
            17:  begin
                sign = t[31:31];
                result = (t >> 2);
                result[31:30] = {sign, sign};
            end
            18:  begin
                sign = t[31:31];
                result = (t >> 8);
                for (i__loop_125 = 5'sb00000 ; i__loop_125 < 5'sb01000 ; i__loop_125 = 5'sb00001 + i__loop_125)
                                sign8[i__loop_125] = sign[1'b0];
                i = i__loop_125;
                result[31:24] = sign8;
            end
            default : begin 
                end
            endcase
            if (result == 32'b00000000000000000000000000000000)
                zero = 1'b1;
            else
                zero = 1'b0;
            r = result;
            z = zero;
        end

endmodule