mux3.v

来自「基于4个mips核的noc设计」· Verilog 代码 · 共 31 行

module MUX3(in0, in1, in2, sel, out);
    input [31:0] in0;
    wire [31:0] in0;
    input [31:0] in1;
    wire [31:0] in1;
    input [31:0] in2;
    wire [31:0] in2;
    input [1:0] sel;
    wire [1:0] sel;
    output [31:0] out;
    reg [31:0] out;
    reg [1:0] sel_t;
    reg [31:0] data;
    
    always @(in0 or in1 or in2 or sel)
        begin : mux_thread
            sel_t = sel;
            if (sel_t == 2'b00)
                data = in0;
            else
            begin
                if (sel_t == 2'b01)
                    data = in1;
                else
                    data = in2;
            end
            out = data;
        end

endmodule